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Single-Bit Processor Enable Scheme

IP.com Disclosure Number: IPCOM000039118D
Original Publication Date: 1987-Apr-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 3 page(s) / 33K

Publishing Venue

IBM

Related People

Downey, JH: AUTHOR [+3]

Abstract

A novel control scheme for selecting and activating processor elements in an array of processor elements is disclosed. Central processing and turnaround time for VLSI circuit designs and groundrule checking is increasing with chip density. Optimization of checking algorithms and hardware performance improvements have not increased at the same rate. A new two-dimensional array processor and address control means is used to optimize computer-aided groundrule checking. The processor consists of an array of single-bit processors called processor elements (PEs). Array density is maximized because each PE is configured with a minimum architecture: an arithmetic and logic unit (ALU), internal registers and control circuits.

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Single-Bit Processor Enable Scheme

A novel control scheme for selecting and activating processor elements in an array of processor elements is disclosed. Central processing and turnaround time for VLSI circuit designs and groundrule checking is increasing with chip density. Optimization of checking algorithms and hardware performance improvements have not increased at the same rate. A new two-dimensional array processor and address control means is used to optimize computer-aided groundrule checking. The processor consists of an array of single-bit processors called processor elements (PEs). Array density is maximized because each PE is configured with a minimum architecture: an arithmetic and logic unit (ALU), internal registers and control circuits. The basic function of an individual PE element is to process data from its internal registers or adjacent PE registers and store the results in an internal register. Previous PE addressing techniques were less effective solutions to the performance problem, for example: 1) Unique addresses generated by the array controller

were used for each PE in the array which

necessitated sequential addressing and global

address bussing.

2) Row and column addressing by the controller

required some sequential addressing since certain

PE array patterns can not be defined in one

address operation.

3) Operations required multiple cycles since enable

flags were used in each PE and were set during

some previous operation. Only certain groups of

PEs whose flags were set could operate during

certain sequences. By using a new addressing technique, each PE receives the same instruction but not all PEs operate during each clock cycle. The PE enable circuitry selects/deselects a PE based on a three-bit field within the instruction and data stored in a PE's registers. Every PE in the array is controlled by its internal data and data contained in the instruction control fields. Operation of each PE is data dependent and individually executed in synchronism...