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General-Purpose Low-End Parallel Bus Interface Circuit Test Fixture

IP.com Disclosure Number: IPCOM000039122D
Original Publication Date: 1987-Apr-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 3 page(s) / 66K

Publishing Venue

IBM

Related People

Prais, MW: AUTHOR

Abstract

A technique is described whereby up to sixteen low-end parallel bus adapter circuit cards, such as are used in the IBM Personal Computer, may be functionally tested simultaneously for static, dynamic and in- situ type of life testing. (Image Omitted) In-situ testing generally involves the monitoring of continuously running circuit applications, while circuit cards are in an environmental testing chamber. In prior art, special fixtures were built to allow a large number of circuit cards to be placed in the chamber, while allowing the controller doing the monitoring to remain outside the chamber. Each time a different card was to be tested, a new interface testing fixture was required.

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General-Purpose Low-End Parallel Bus Interface Circuit Test Fixture

A technique is described whereby up to sixteen low-end parallel bus adapter circuit cards, such as are used in the IBM Personal Computer, may be functionally tested simultaneously for static, dynamic and in- situ type of life testing.

(Image Omitted)

In-situ testing generally involves the monitoring of continuously running circuit applications, while circuit cards are in an environmental testing chamber. In prior art, special fixtures were built to allow a large number of circuit cards to be placed in the chamber, while allowing the controller doing the monitoring to remain outside the chamber. Each time a different card was to be tested, a new interface testing fixture was required. The fixture described herein provides for the in-situ testing of circuit cards, thereby eliminating the need for a special interface fixture for each new circuit card. The fixture is unique in that the data is written into all the cards under test simultaneously, but the data from only one card is gated

(Image Omitted)

onto the data bus of the controller during a read so as to monitor only the cards under test sequentially. Failures are then recorded on a realtime basis. The fixture consists of three basic elements: a driver card, a receiver card and a backplane card, as shown in Fig. 1. An IBM Personal Computer (PC) AT is used as the controller and contains the driver card which connects to a sixteen- position circuit card holder by means of coax cables. A receiver circuit card is included in each circuit card holder which buffers the received signals prior to distributing the signals to the sixteen individual circuit cards. The cards to be tested are inserted into a backplane card which has a decoder for gating the output data from only one circuit card at a time.

(Image Omitted)

The driver card has five major buses: data bus, address bus, output control bus, input control bus and a bidirectional control bus, as shown in the block diagram of Fig. 2. Data bus enable logic unit 10 is provided to determine if the data transfer is to a card under test, and, if so, enables data bus 11 through bidirectional buffer unit 12. The data bus enable logic unit 10 is controlled by the input/output (I/O) and memory addresses used by the circuit cards under test. Since the test...