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High Speed Data Format Converter Circuit

IP.com Disclosure Number: IPCOM000039127D
Original Publication Date: 1987-Apr-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 2 page(s) / 73K

Publishing Venue

IBM

Related People

Chang, PT: AUTHOR [+3]

Abstract

A circuit has been proposed to provide the narrow pulse widths required for array test systems used in semiconductor device manufacturing schemes. The multiplexing technique proposed may be used in any application where subnanosecond pulse widths are required. Conventional format converter circuits using an 11C70 flip-flop cannot produce a minimum pulse width below 1.5 nanoseconds. The array test system requires high speed formated data, as indicated in the timing diagram of Fig. 1. The minimum output pulse width required by the array test system should be less than 1.0 ns in the worst scenario. (Image Omitted) The multiplexing scheme of Fig. 2 is applied in the new circuit as a basic concept.

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High Speed Data Format Converter Circuit

A circuit has been proposed to provide the narrow pulse widths required for array test systems used in semiconductor device manufacturing schemes. The multiplexing technique proposed may be used in any application where subnanosecond pulse widths are required. Conventional format converter circuits using an 11C70 flip-flop cannot produce a minimum pulse width below 1.5 nanoseconds. The array test system requires high speed formated data, as indicated in the timing diagram of Fig. 1. The minimum output pulse width required by the array test system should be less than 1.0 ns in the worst scenario.

(Image Omitted)

The multiplexing scheme of Fig. 2 is applied in the new circuit as a basic concept. The data flip-flops (D-FFs), or data latches, are clocked out of phase at 1/2 the system rate to permit formatting individually at T1 timing and multiplexing to the previously reset (or set) other output at T2 timing. This allows data widths to go essentially to zero at system rates twice as fast as the maximum latch rate. The high speed multiplexer (MUX) performs as a SPDT (single-pole, double- throw) switch which restores the final output speed with formatter data, as indicated in Fig. 3. A schematic diagram of the multiplexed format converter is indicated in Fig. 4. The new circuit consists of three basic functional blocks: Demultiplexer, Multiplexer, and RZ/R1 mode control circuits. The input pulse T, an externally programmable l...