Browse Prior Art Database

Multiple Arithmetic Processors Within a Functional Co-Processor

IP.com Disclosure Number: IPCOM000039148D
Original Publication Date: 1987-Apr-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 2 page(s) / 54K

Publishing Venue

IBM

Related People

Danen, RJ: AUTHOR [+2]

Abstract

The use of a Restricted Instruction Set Computer (RISC) architecture, differing from the typical Von Neumann serial processing approach, allows simultaneous pipelining and processing of non-dependent data functions in a multiple processor (co-processor) environment. This approach is advanced by the use of multiple arithmetic execution units within one such co-processor. This co-processor is the Engineering Scientific Accelerator Floating Point Unit (ESA FPU) used in mid-range pipeline processors. This simultaneous execution is accomplished as described in the following. Illustrated in Fig. 1 is a simplified configuration of the mid- range pipeline processor.

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Multiple Arithmetic Processors Within a Functional Co-Processor

The use of a Restricted Instruction Set Computer (RISC) architecture, differing from the typical Von Neumann serial processing approach, allows simultaneous pipelining and processing of non-dependent data functions in a multiple processor (co-processor) environment. This approach is advanced by the use of multiple arithmetic execution units within one such co-processor. This co- processor is the Engineering Scientific Accelerator Floating Point Unit (ESA FPU) used in mid-range pipeline processors. This simultaneous execution is accomplished as described in the following. Illustrated in Fig. 1 is a simplified configuration of the mid- range pipeline processor. Two co-processors are shown as blocks (Instruction Processing Unit (IPU) 1 and Floating Point (FPU) Unit 2 with the system-dependent S/370 Emulation Assist Processor 3 and the various storage and input/output functional blocks which make up the remainder of the processing system. Operation of the IPU 1 and FPU 2 co-processors is designated by the order of the instruction stream which is normally accessed from program memory with instructions sourced from the Instruction Cache 4 and data from the Data Cache 5. The IPU 1 normally reads the instructions and data then passes them on to the co-processor (FPU 2) when applicable. In the case of the mid-range pipeline processor, the Emulation Assist Processor (EAP) 3 is added to take both instructions a...