Browse Prior Art Database

Auto-Align Standard Setup Wafer

IP.com Disclosure Number: IPCOM000039189D
Original Publication Date: 1987-May-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 2 page(s) / 44K

Publishing Venue

IBM

Related People

Leone, E: AUTHOR [+4]

Abstract

Disclosed is a method to reduce the pre-alignment time required by a commercial align-expose system with auto align used for processing semiconductor wafers.. A special setup wafer has been designed with three widely spaced pairs of auto-align targets. Only one wafer stage position exists which can work properly, and with this all three sets may be properly centered within the acquisition zone by fine tuning adjustments. Previous methods of wafer setup referenced the wafer stage to the mask stage, physically centering the wafer stage movement in X, Y and r axes. With such an approach, tool-to-tool or masterslice-to-masterslice variations could occur.

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Auto-Align Standard Setup Wafer

Disclosed is a method to reduce the pre-alignment time required by a commercial align-expose system with auto align used for processing semiconductor wafers.. A special setup wafer has been designed with three widely spaced pairs of auto-align targets. Only one wafer stage position exists which can work properly, and with this all three sets may be properly centered within the acquisition zone by fine tuning adjustments. Previous methods of wafer setup referenced the wafer stage to the mask stage, physically centering the wafer stage movement in X, Y and r axes. With such an approach, tool-to-tool or masterslice-to-masterslice variations could occur. Because target locations vary from product type to product type, depending on chip size, it is necessary to have a proper wafer stage alignment to ensure that the target for each product will fall into the center of the viewing optics acquisition zone. Using the previous alignment method, the desired wafer stage positions may vary significantly due to tolerances in tool setup. With the proposed method, a standard wafer is generated according to a mathematical model which depicts the align tool geometry (Fig. 1). Only one wafer stage position, X, Y, r, exists which will perfectly satisfy this geometry. The standard wafer (Fig. 2) is printed with three widely spaced pairs of targets so that a more accurate wafer stage alignment may be achieved. When properly positioned, it is possible to...