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Threshold Logic Circuit

IP.com Disclosure Number: IPCOM000039190D
Original Publication Date: 1987-May-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 2 page(s) / 26K

Publishing Venue

IBM

Related People

Geneste, M: AUTHOR [+2]

Abstract

The circuit shown in the drawing allows the detection of 5, 7 or 8 bits ON in an 8-bit word to be performed in a minimum of cells and logic layers. Two identical cells 1 and 2 receive four bits of the words and generate at their output the four states: State 1 = 1 out of 4 bits ON State 2 = 2 out of 4 bits ON State 3 = 3 out of 4 bits ON State 4 = 4 bits ON Cell 3 receives the outputs of cells 1 and 2 and generates therefrom three states: State 5 = 5 out of 8 bits ON State 6 = 7 out of 8 bits ON State 7 = 8 bits ON The logic implementation of cells 1 and 2 is based on the following truth table which indicates the number of bits ON among the 16 possible combinations of four bits: Cells 1 and 2 have four outputs X1, X2, X3, X4 and Y1, Y2, Y3, Y4, respectively.

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Threshold Logic Circuit

The circuit shown in the drawing allows the detection of 5, 7 or 8 bits ON in an 8-bit word to be performed in a minimum of cells and logic layers. Two identical cells 1 and 2 receive four bits of the words and generate at their output the four states: State 1 = 1 out of 4 bits ON State 2 = 2 out of 4 bits ON

State 3 = 3 out of 4 bits ON

State 4 = 4 bits ON Cell 3 receives the outputs of cells 1 and 2 and generates therefrom three states: State 5 = 5 out of 8 bits ON State 6 = 7 out of 8 bits ON

State 7 = 8 bits ON The logic implementation of cells 1 and 2 is based on the following truth table which indicates the number of bits ON among the 16 possible combinations of four bits: Cells 1 and 2 have four outputs X1, X2, X3, X4 and Y1, Y2, Y3, Y4, respectively. Assuming that their inputs are ABCD and A'B'C'D', the output signals result from the following logical equations: The same equations exist between Y1, Y2, Y3 and Y4 and A'B'C'D', respectively. The truth table of cell 3 is the following: The signal on outputs Z5, Z7 and Z8 of cell 3 is indicative of states 5, 7 and 8, respectively, with: Z5 = X1Y4 + X2Y3 + X3Y2 + X4Y1

Z7 = X4Y3 + Y4X3

Z8 = X4Y4

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