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Fast Level Converter Circuit

IP.com Disclosure Number: IPCOM000039193D
Original Publication Date: 1987-May-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 2 page(s) / 27K

Publishing Venue

IBM

Related People

Loehlein, WD: AUTHOR [+2]

Abstract

Proposed is a level converter/receiver circuit which improves the turn-off time, while avoiding reliability problems caused by high voltage stress. As the technological progress, for instance, for semiconductor memories and logic proceeds at a different pace, the situation may arise that different supply voltages have to be provided for two or more types of such interacting circuit parts. Memories, for instance, may require 3.4 V, while the logic still needs a supply voltage of 5.5 V. At the low level/high level system interface, switching time and voltage stress problems have to be considered for standard level converter circuits which substantially consist of a serial transistor pass gate followed by an output (inverter) driver stage.

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Fast Level Converter Circuit

Proposed is a level converter/receiver circuit which improves the turn-off time, while avoiding reliability problems caused by high voltage stress. As the technological progress, for instance, for semiconductor memories and logic proceeds at a different pace, the situation may arise that different supply voltages have to be provided for two or more types of such interacting circuit parts. Memories, for instance, may require 3.4 V, while the logic still needs a supply voltage of 5.5 V. At the low level/high level system interface, switching time and voltage stress problems have to be considered for standard level converter circuits which substantially consist of a serial transistor pass gate followed by an output (inverter) driver stage. The proposed receiver, differing from state-of-the- art devices by the addition of capacitor C7 and transistors T4 to T6, is shown in the figure. This receiver improves the turn-off time by permitting node A to go up to quickly discharge the output. As soon as the output goes down, node A is returned to the normal high level to avoid voltage stress. The receiver operates in detail as follows. Assume the input is initially low, then T4 is on, keeping node B at 3.4 V. Node A is down, as T1 is on. The output goes up to 3.4 V, turning off T6. Voltage limiter T5 is off. When the input signal goes up from 0 to 5.5 V, then T4 is turned off. Node B is boosted and limited to 3.4 V VT in response to capacitor C7...