Browse Prior Art Database

High Performance Floating Point Register Parity Checking

IP.com Disclosure Number: IPCOM000039199D
Original Publication Date: 1987-May-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 4 page(s) / 60K

Publishing Venue

IBM

Related People

Hrusecky, DA: AUTHOR

Abstract

To increase error detection capability in floating point registers (FPR), parity should be stored and checked upon data access. In floating point units (FPUs) with FPRs preceded by high speed postnormalization shifters, parity generation may not be possible. A selective check table that allows parity checking on all of the FPR array hardware is described in the following. Essential to the data integrity of any array is the storing and subsequent checking of parity for the data in the array. The FPR array stores data in a floating point format (Fig. 1), specifically one sign bit, 7 characteristic bits, and 24 fraction bits for short precision or 56 fraction bits for long precision. Note that a characteristic is an exponent biased by + 64.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 39% of the total text.

Page 1 of 4

High Performance Floating Point Register Parity Checking

To increase error detection capability in floating point registers (FPR), parity should be stored and checked upon data access. In floating point units (FPUs) with FPRs preceded by high speed postnormalization shifters, parity generation may not be possible. A selective check table that allows parity checking on all of the FPR array hardware is described in the following. Essential to the data integrity of any array is the storing and subsequent checking of parity for the data in the array. The FPR array stores data in a floating point format (Fig. 1), specifically one sign bit, 7 characteristic bits, and 24 fraction bits for short precision or 56 fraction bits for long precision. Note that a characteristic is an exponent biased by + 64.

(Image Omitted)

Because this concept is currently implemented in a high performance Engineering Scientific Accelerator (ESA) FPU design, an overview of its details is provided. The future of floating point designs is such that they will require chips of higher density to increase performance, and the ESA is typical of this trend. Also, critical to the performance of a FPU is the time required to write data into its FPR, since this action occurs in almost every instruction. These designs should locate a postnormalization shifter in the same chip with the FPRs to reduce off- chip signal transfer time. Thus, time can not be wasted on the "luxury" of FPR parity generating. Fig. 2 shows the layout of the ESA. The chip where the FPR resides also contains hardware for pre/postnormalization of fractions, exponent manipulation logic, and the status word register. Thus, the chip has very limited space to include FPR parity generate/check features. The chip has just enough room for generate or check functions for each byte of data, but not enough room for both generate and check functions.

(Image Omitted)

Furthermore, because the results of floating point arithmetic instructions to be stored in the FPR must go through the leading zero detection logic (LZD), postnorm shifter, and exponent adjustment, the parity for this data could not be generated in time (Fig. 3). Limited I/O's were another constraint, in that the FPR data and its parity could not be shipped off to a neighboring, less populated chip to do the check function. Thus a "selective FPR check table" was implemented on the neighboring control chip to get around these problems. The "selective FPR check table" is built from high speed registers to form a small three-by-eight array. The three bits across the table correspond to the upper exponent, upper fraction, and lower fraction portions of the FPR data and the eight rows correspond to the eight FPR addresses as implemented in the ESA. The input to the R REG connects to the main bus upon which the unpostnormalized fraction results from the ADD, Multiply and Divide chips arrive. Also, when a Load operation

(Image Omitted)

is performed, receivin...