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Interlock for Staggered Starting of Motor Generator Sets in Multi-Processing System

IP.com Disclosure Number: IPCOM000039211D
Original Publication Date: 1987-May-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 2 page(s) / 32K

Publishing Venue

IBM

Related People

Park, G: AUTHOR [+2]

Abstract

In large multi-processing systems, each Central Electronics Complex (CEC) is supported by a Power Distribution Frame (PDF). In some installations each PDF controls a pair of Motor Generators (MGs) which are required to convert utility 50/60 Hz power to the 400 Hz power needed by the CEC power supplies. The MG control circuit sequences the pair such that the second MG starts when the first has reached normal speed. Each MG requires twice its normal running current from initial start time until half the time before normal speed is reached. The problem to be solved is to request each MG control circuit to start its sequence so that both pairs of MGs can be stagger-started to minimize utility loading, in response to varying requests to power on either or both of the CECs.

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Interlock for Staggered Starting of Motor Generator Sets in Multi- Processing System

In large multi-processing systems, each Central Electronics Complex (CEC) is supported by a Power Distribution Frame (PDF). In some installations each PDF controls a pair of Motor Generators (MGs) which are required to convert utility 50/60 Hz power to the 400 Hz power needed by the CEC power supplies. The MG control circuit sequences the pair such that the second MG starts when the first has reached normal speed. Each MG requires twice its normal running current from initial start time until half the time before normal speed is reached. The problem to be solved is to request each MG control circuit to start its sequence so that both pairs of MGs can be stagger-started to minimize utility loading, in response to varying requests to power on either or both of the CECs. The drawing shows an interlock circuit that allows two Console Power Initializers (CPIs) to properly meet the above requirement in response to requests made via operator power on/off switches. Latch 1 is set when a control panel switch Power On is operated to start the MG sets of one CPI. Latch 2 is set on the coincidence of the set state of latch 1 and the down level of a signal Start Request on a line 3 from the other CPI. An up level of Start Request 3 inhibits setting latch 2 and thereby inhibits other components of the drawing from starting an MG set. When latch 2 is set, its output is transmitted through an AN...