Browse Prior Art Database

Enhanced Transverse Via/Transtrip

IP.com Disclosure Number: IPCOM000039214D
Original Publication Date: 1987-May-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 2 page(s) / 67K

Publishing Venue

IBM

Related People

Gow, J: AUTHOR

Abstract

This article relates to packaging semiconductor chips on a ceramic carrier, combining punch-and-fill techniques of multilayer ceramic [1] carrier fabrication with transverse via/transtrip [2] ceramic carrier technology, allowing more degrees of output freedom. A multilayer ceramic chip carrier package (exploded view shown in Fig. 1) is fabricated by stacking a set of personalized ceramic greensheets (sheets before firing) together. Each sheet in the stack is personalized by silk screen or photolithographic techniques to form conductor lines and a via grid of holes is punched and filled with a metallic paste to interconnect the layers. The set is subsequently fired, causing the sheets to cure and fuse together, forming a multilevel wiring semiconductor chip carrier.

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Enhanced Transverse Via/Transtrip

This article relates to packaging semiconductor chips on a ceramic carrier, combining punch-and-fill techniques of multilayer ceramic [1] carrier fabrication with transverse via/transtrip [2] ceramic carrier technology, allowing more degrees of output freedom. A multilayer ceramic chip carrier package (exploded view shown in Fig. 1) is fabricated by stacking a set of personalized ceramic greensheets (sheets before firing) together. Each sheet in the stack is personalized by silk screen or photolithographic techniques to form conductor lines and a via grid of holes is punched and filled with a metallic paste to interconnect the layers. The set is subsequently fired, causing the sheets to cure and fuse together, forming a multilevel wiring semiconductor chip carrier. The carrier is pinned and at least one semiconductor chip is mounted on top. Information flow is from input to output (top to bottom), as shown in Fig. 2. A transverse via/transtrip module or chip carrier package is fabricated by laminating screened greensheets normal to the direction of punched and filled sheets in a multilayer carrier. An exploded view is shown in Fig. 3, where individual plys of greensheets are aligned and stacked on end such that, after an appropriate cutting operation, the top edge of the greensheets exhibits an array of conductor ends on a predetermined grid and the bottom edge of the greensheets exhibits another grid of predetermined conductor e...