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Vlsi Technologies Retrograded Source/Drain Junctions

IP.com Disclosure Number: IPCOM000039229D
Original Publication Date: 1987-May-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 2 page(s) / 63K

Publishing Venue

IBM

Related People

Troutman, RR: AUTHOR

Abstract

Retrograded source/drain junctions reduce hot carrier reliability effects and field-effect transistor (FET) series spreading resistance. A high lateral electric field is associated with the conventional FET drain diffusion, especially arsenic diffusions which cause hot carrier effects. The utilization of graded junctions, such as lightly doped drains (LDDs) and lightly implanted silicided drains, as solutions to this problem result in degraded performance due to increased series resistance. This series resistance, caused by spreading resistance from the channel region to drain contact, is increased by shorter channels, thinner oxides and shallow junctions.

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Vlsi Technologies Retrograded Source/Drain Junctions

Retrograded source/drain junctions reduce hot carrier reliability effects and field-effect transistor (FET) series spreading resistance. A high lateral electric field is associated with the conventional FET drain diffusion, especially arsenic diffusions which cause hot carrier effects. The utilization of graded junctions, such as lightly doped drains (LDDs) and lightly implanted silicided drains, as solutions to this problem result in degraded performance due to increased series resistance. This series resistance, caused by spreading resistance from the channel region to drain contact, is increased by shorter channels, thinner oxides and shallow junctions. A substantial performance degradation in the FET CMOS technology is attributable to source/drain spreading resistance, and continued scaling for higher density devices will exacerbate the problem. A new approach is the retrograded source/drain which reduces spreading resistance without creating hot carrier reliability problems. By placing the buried peak lateral electric field below the surface as shown in Fig. 1, any hot carriers generated will have time to scatter and cool as they travel toward the surface. The depth of the buried peak field is chosen to eliminate gate current for the maximum voltage to be experienced on the FET. When an FET is in saturation, the channel near the drain leaves the surface and electrons enter the drain diffusion in the vicini...