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Browse Prior Art Database

Alternative Method of Making Self-Aligned MESFET Transistors

IP.com Disclosure Number: IPCOM000039236D
Original Publication Date: 1987-May-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 3 page(s) / 64K

Publishing Venue

IBM

Related People

Nguyen, TN: AUTHOR [+2]

Abstract

This publication describes a method for fabricating self-aligned gate MESFETs using sidewall spacers and with a broader metallurgy choice and a single contact metallization step. Its main features are that the source and drain implant anneal at high temperatures is done prior to the gate, source, and drain metallization. This removes the requirement of a high-temperature gate material for self-aligned transistors and allows the use of many low-temperature metals that were not possible before. Also, the metal contacts to the gate, source, and drain are fabricated in a single step; in contrast, standard self-aligned FET processes normally require two steps, one for gate formation as a self- alignment mask and a second for contact deposition. (Image Omitted) The key steps of the method are explained below: 1. Fig.

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Alternative Method of Making Self-Aligned MESFET Transistors

This publication describes a method for fabricating self-aligned gate MESFETs using sidewall spacers and with a broader metallurgy choice and a single contact metallization step. Its main features are that the source and drain implant anneal at high temperatures is done prior to the gate, source, and drain metallization. This removes the requirement of a high-temperature gate material for self-aligned transistors and allows the use of many low-temperature metals that were not possible before. Also, the metal contacts to the gate, source, and drain are fabricated in a single step; in contrast, standard self-aligned FET processes normally require two steps, one for gate formation as a self- alignment mask and a second for contact deposition.

(Image Omitted)

The key steps of the method are explained below:

1. Fig. 1 shows the cross-sectional view of a

transistor region which has been defined by a

planar isolation technique, such as shallow trench

for Si or proton bombardment for GaAs devices. A

layer of CVD (chemical vapor deposited) oxide is

deposited and to be used as a mask for source and

drain implants. Its thickness should be 1000

Angstroms or more depending on the technology.

2. The source and drain contact holes are delineated

by a combination of lithography and reactive-ion

etch of the CVD oxide. A CVD nitride layer is

deposited and then reactive-ion etched to form a

nitride sidewall around the perimeter of the

contact holes. Dopant implantation is carried out

to form heavily doped junctions which are

self-aligned to the contact holes. The dopants

are activated by an anneal, and the results are

illustrated in Fig. 2.

3. The gate electrode is now defined by lithography.

The openings of the gate mask should overlap the

source and drain diffusions, but critical

alignment is not required. The CVD oxide between

source and drain is then removed by a wet etch,

leaving the nitride sidewalls intact; these serve

to define the se...