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Analysis of Logic Path Timing Using Block-Oriented Delay Analysis Algorithm

IP.com Disclosure Number: IPCOM000039237D
Original Publication Date: 1987-May-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 2 page(s) / 43K

Publishing Venue

IBM

Related People

Langenbahn, MD: AUTHOR

Abstract

A forward trace algorithm has been previously described [*]. The inclusion of a step in this forward trace algorithm of a block-oriented delay analysis to determine if a block has already been processed prevents the redundant processing of the block in the event of multiple paths. If a circuit contains a loop, this step would be essential to stop the processing. The forward trace part of the algorithm is in the block diagram. Reference "Analysis of Logic Path Timing," IBM Technical Disclosure Bulletin10A, 5499-5500 (March 1985).

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Analysis of Logic Path Timing Using Block-Oriented Delay Analysis Algorithm

A forward trace algorithm has been previously described [*].

The inclusion of a step in this forward trace algorithm of a block-oriented delay analysis to determine if a block has already been processed prevents the redundant processing of the block in the event of multiple paths. If a circuit contains a loop, this step would be essential to stop the processing. The forward trace part of the algorithm is in the block diagram. Reference "Analysis of Logic Path Timing," IBM Technical

Disclosure Bulletin10A, 5499-5500 (March 1985).

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