Browse Prior Art Database

Divide-By-3 Clock Generator With Mini Wait States

IP.com Disclosure Number: IPCOM000039248D
Original Publication Date: 1987-May-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 2 page(s) / 54K

Publishing Venue

IBM

Related People

Schmitt, SA: AUTHOR

Abstract

This invention allows the use of slow dynamic memories with a fast processor. The problem solved by this invention is the use of 175-nsecond dynamic memories with a 10-megahertz Motorola 68000 processor. In this case the memory is slightly slower than the processor so the processor had to be wait-stated. By using standard design techniques for wait- states, the processor would have been slowed down by 25%. The solution embodied in this invention uses much smaller wait-states and only slows the processor by 4%. Fig. 1 shows the logic diagram for the clock generator. It is a fundamental mode circuit with five state-variables of Y1 through Y5. The state-variables Y1, Y2 and Y3 form a shift register which divides the input oscillator by three.

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Divide-By-3 Clock Generator With Mini Wait States

This invention allows the use of slow dynamic memories with a fast processor. The problem solved by this invention is the use of 175-nsecond dynamic memories with a 10-megahertz Motorola 68000 processor. In this case the memory is slightly slower than the processor so the processor had to be wait- stated. By using standard design techniques for wait- states, the processor would have been slowed down by 25%. The solution embodied in this invention uses much smaller wait-states and only slows the processor by 4%. Fig. 1 shows the logic diagram for the clock generator. It is a fundamental mode circuit with five state-variables of Y1 through Y5. The state-variables Y1, Y2 and Y3 form a shift register which divides the input oscillator by three. The input oscillator is 30 megahertz so the state-variables Y1, Y2 and Y3 change at a 10-megahertz rate. State- variable Y3 is the clock for the Motorola 68000.

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The pause input causes the circuit to lengthen one cycle of the state-variables by one half of the input oscillator period or 17 nseconds. In practice, the pause input is pulsed whenever it is desired to slow the processor down to allow for the longer memory access. At most, there will be one pause every 400 nseconds which results in a 4% decrease in processor speed. Standard practice would wait-state the 68000 for one period of its input clock or 100 nseconds which is a 25% slowdown. Fig. 2 shows the ti...