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LSSD Circuitry for Latching Signals Shorter Than the Clock Period

IP.com Disclosure Number: IPCOM000039279D
Original Publication Date: 1987-May-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 2 page(s) / 33K

Publishing Venue

IBM

Related People

Engbersen, AJ: AUTHOR

Abstract

This article suggests a variant of LSSD (level sensitive scan design) circuitry to allow the handling of fast data signals and to increase testability. In normal LSSD-type circuitry, signals are transferred into latches under control of a system clock (C). To enable the latching of data signals having pulses shorter than the system clock period, one would have to provide a faster clock and, consequently, the whole circuitry would have to be able to handle signals of higher speed.

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LSSD Circuitry for Latching Signals Shorter Than the Clock Period

This article suggests a variant of LSSD (level sensitive scan design) circuitry to allow the handling of fast data signals and to increase testability. In normal LSSD-type circuitry, signals are transferred into latches under control of a system clock (C). To enable the latching of data signals having pulses shorter than the system clock period, one would have to provide a faster clock and, consequently, the whole circuitry would have to be able to handle signals of higher speed. If only for a limited number of circuit blocks such fast data signals are expected, the provision of faster clocks and higher-speed circuitry can be avoided by the invention which suggests to provide for such limited number of circuit blocks: (a) additional circuitry for deriving a latching pulse from the edge of a data signal (so that this latching pulse instead of the system clock can be used for latching); (b) a select circuit for enabling either the derived latching pulse or the system clock pulse for latching; (c) an extra latch for latching the output signal of the additional circuitry, so that this additional circuitry could also be tested; and (d) further circuitry to interrupt for testing purposes a portion of the additional circuitry. In the figure, the modified LSSD circuitry is shown. The input signal S(IN) is admitted to the circuitry under control of the signal CTL by gate A1. During normal operation (non-manufacturing tests) the test latch FF1 will receive at input D a logic, high input signal (+V) and thus furnish a logic high output signal which conditions gate A2. The input signal S(IN) will propagate from A1 to gate G3 along two paths: thro...