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Browse Prior Art Database

High Speed On-Chip Addressable Memory Clock

IP.com Disclosure Number: IPCOM000039290D
Original Publication Date: 1987-May-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 3 page(s) / 44K

Publishing Venue

IBM

Related People

Broockman, EC: AUTHOR

Abstract

Disclosed is a level sensitive scan design (LSSD) type of testable circuit that provides timing for an on-chip clocked addressable memory. The circuit comprises a register bank of latches 1 and an equality circuit group 2. In concept, the latch size L1 and L2 of the registers feed a simple equality comparator 5. Non-overlapping clock signals C1 (Image Omitted) and C2 set the latch state L1 and transfer it to L2, respectively. When the C1 clock turns on the L1 side of the latches, the equality comparator 5 will change state. Following the C1 clock cycle, the C2 clock cycle will be applied, and as data in the L2 side of latches 4 stabilizes, the equality comparator 5 will again change states. The series of state changes in the equality comparator 5 provides clocking for on-chip addressable memory.

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High Speed On-Chip Addressable Memory Clock

Disclosed is a level sensitive scan design (LSSD) type of testable circuit that provides timing for an on-chip clocked addressable memory. The circuit comprises a register bank of latches 1 and an equality circuit group 2. In concept, the latch size L1 and L2 of the registers feed a simple equality comparator 5. Non-overlapping clock signals C1

(Image Omitted)

and C2 set the latch state L1 and transfer it to L2, respectively. When the C1 clock turns on the L1 side of the latches, the equality comparator 5 will change state. Following the C1 clock cycle, the C2 clock cycle will be applied, and as data in the L2 side of latches 4 stabilizes, the equality comparator 5 will again change states. The series of state changes in the equality comparator 5 provides clocking for on-chip addressable memory. The AND gate 6 senses stabilization of the signals from the comparator 5 attached to each pair of latches 3 and 4 in the register 1. The overall group of comparator 5 may be referred to as the comparator circuit 2. When the comparator circuit is stable at a given condition, the AND gate 6 will be enabled and provide an output clock pulse for the on-chip addressable memory. The T flip-flop circuit 7 is utilized to differentiate between different cycle accesses and changes state in accordance with the changes of state in the last cell of the register 1 to which it is appended. Typically, the register 1 in Fig. 1 may be embodied as an address register for an on-chip addressable memory. The memory requires that the address be stable prior to being stroked or clocked in order to

(Image Omitted)

provide accurate access to memory locations. Typically, the set-up time in the latches in the register 1 is extremely short. Thus, as soon as the address is stable, the addressable memory should be selected for the highest speed performance applications. The address is known to be stable once the address data has propagated through to the L2 side 4 of the register 1 in each latch. The equality circuit 2 compares the states of the L1 and L2 sides 3 and 4 of each latch cell in the register 1. When these latches show equivalents, the address is stable and the on-chip addressable memory may be clocked. In many applications, a given addressable address location may be sequentially accessed. The T flip-flop circuit 7 is appended to the register bank 1 to differentiate between separate accesses to the same address. That is, the address will actually have to be presented to the register 1 twice to have two separate accesses to the same address location in the addressable memory. In practice, in level sensitive scan design circuits in which latches are set on the attainment of the voltage level instead of at the edge of an ongoing pulse, the latch portions L1, L2, shown as 3 and 4 of a given...