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Differential AMPLIFIER

IP.com Disclosure Number: IPCOM000039296D
Original Publication Date: 1987-May-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 2 page(s) / 49K

Publishing Venue

IBM

Related People

Hoffman, CR: AUTHOR

Abstract

This article describes a structure for a CMOS operational amplifier in which a biasing device and differential pair devices are placed in separate N-wells on a P substrate. By using two N-wells, the common mode range and the small signal gain of the amplifier area increased beyond that of a one N-well design. Fig. 1 shows an input stage for a typical CMOS differential AMPLIFIER. DEVICE T1 (P AND N INDICATE THE TYPES OF DEVICES) IS A CURRENT source providing a bias current to the differential pair T2A and T2B, respectively. The differential signal, Vdif, is amplified and converted to a single-ended signal, Vout . The gain of the circuit may be expressed as follows: Av = gm2 / (go2+go4) (1) (Image Omitted) where gm2 = transconductance of T2 go = small signal output conductance.

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Differential AMPLIFIER

This article describes a structure for a CMOS operational amplifier in which a biasing device and differential pair devices are placed in separate N-wells on a P substrate. By using two N-wells, the common mode range and the small signal gain of the amplifier area increased beyond that of a one N-well design. Fig. 1 shows an input stage for a typical CMOS differential AMPLIFIER. DEVICE T1 (P AND N INDICATE THE TYPES OF DEVICES) IS A CURRENT source providing a bias current to the differential pair T2A and T2B, respectively. The differential signal, Vdif, is amplified and converted to a single-ended signal, Vout . The gain of the circuit may be expressed as follows: Av = gm2 / (go2+go4)
(1)

(Image Omitted)

where gm2 = transconductance of

T2

go = small signal output conductance. The small signal voltage gain will be maintained as long as the transistors T2A and T2B, T3 and T4 remain in their saturation region and the bias current, set by T1, is relatively constant. To insure that a desired T1 bias current is maintained, Vsd1 cannot fall below a predetermined voltage level. Also, to insure that T2A and T2B remain on the source-to-gate voltage, Vsg2 must exceed the threshold voltage (Vth2) by an amount sufficient to support current in T2. The quantity Vsg minus the absolute value of Vth is known as the overdrive voltage, Vod. From Fig. 1 it can be seen that for the case where Vdif = 0, the common mode voltage can be expressed as Vcm = VH - Vsd1...