Browse Prior Art Database

Semiconductor Integrated Display

IP.com Disclosure Number: IPCOM000039314D
Original Publication Date: 1987-May-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 2 page(s) / 70K

Publishing Venue

IBM

Related People

Cowburn, AR: AUTHOR [+3]

Abstract

European Patent Application 0112417-A1 describes a semiconductor integrated display of the electrochromic or liquid crystal type having a semiconductor substrate with an addressable matrix of transistors integrated therein. A corresponding array of picture element (pel) display electrodes is formed over the transistor matrix after providing electrical connection vias in an intermediate insulating layer. This disclosure describes modification to the above structure to provide improved yield and performance. The basic change is to offset each driving transistor with respect to its associated electrode. The starting point of the process is as described in the above (Image Omitted) European Patent Application - a silicon substrate carrying an array of FETs with drain (D) metal contacts exposed.

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Semiconductor Integrated Display

European Patent Application 0112417-A1 describes a semiconductor integrated display of the electrochromic or liquid crystal type having a semiconductor substrate with an addressable matrix of transistors integrated therein. A corresponding array of picture element (pel) display electrodes is formed over the transistor matrix after providing electrical connection vias in an intermediate insulating layer. This disclosure describes modification to the above structure to provide improved yield and performance. The basic change is to offset each driving transistor with respect to its associated electrode. The starting point of the process is as described in the above

(Image Omitted)

European Patent Application - a silicon substrate carrying an array of FETs with drain (D) metal contacts exposed. This substrate is sputtered with quartz and followed by vapor-deposited silicon nitride. Resist is applied, exposed and developed, followed by a reactive ion etch (RIE) to form a via hole through the quartz/nitride layer to the "D" metal. The resist is removed, and Fig. 1 shows the result. Successive Ti, Au and Cr layers are evaporated over the surface. A resist is applied, exposed and developed, and given three consecutive wet etches to remove unwanted areas of Ti, Au and Cr and leave an H metal interconnection. Stripping the resist gives Fig. 2 (substrate omitted). Next, Fig. 3 shows the structure after applying polyimide 1 consisting of four...