Browse Prior Art Database

Method for Testing Embedded Shift Register in a DRAM Chip

IP.com Disclosure Number: IPCOM000039330D
Original Publication Date: 1987-May-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Fitzgerald, BF: AUTHOR [+3]

Abstract

Using data written into an array as a test on the functionality of the refresh address counter is reported. Many dynamic random-access memories (DRAMs) have a refresh address counter on the chip which is usually architected as a shift register (SR). Because the SR is usually an integral part of the addressing circuits, it is not accessible to the outside of the chip, which makes a functionality test of the refresh counter circuit difficault and time consuming. The conventional method of testing the refresh address counter circuits has been to write the memory array to a high level (1's) and then pause to force the SR to refresh the array. After many refresh cycles have taken place, the array is read out and scanned for unique fail patterns related to the refresh address counter.

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Method for Testing Embedded Shift Register in a DRAM Chip

Using data written into an array as a test on the functionality of the refresh address counter is reported. Many dynamic random-access memories (DRAMs) have a refresh address counter on the chip which is usually architected as a shift register (SR). Because the SR is usually an integral part of the addressing circuits, it is not accessible to the outside of the chip, which makes a functionality test of the refresh counter circuit difficault and time consuming. The conventional method of testing the refresh address counter circuits has been to write the memory array to a high level (1's) and then pause to force the SR to refresh the array. After many refresh cycles have taken place, the array is read out and scanned for unique fail patterns related to the refresh address counter. The test time, tester temperature variations and variability of chip leakage make a new approach to testing the refresh address counter highly desirable. By employing a test that causes data to be written into an array on all bit lines as a function of the refresh address counter, a check is made which guarantees the functionality of the counter in a minimum amount of time. The test employs the DRAM array as a medium for holding data, allowing the SR to self-test. The test sequence follows: 1) Write the array to a "1" level.

2) Activate the refresh address counter test circuit,

causing every refresh cycle to write a "0" into

all bi...