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Program for Generating a Fault MODEL of a Differential Cascode Emitter-Coupled LOGIC Tree

IP.com Disclosure Number: IPCOM000039334D
Original Publication Date: 1987-May-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 3 page(s) / 63K

Publishing Venue

IBM

Related People

Leet, DG: AUTHOR

Abstract

A program is described which defines a near minimum number of logic blocks required for a fault model of a differential cascode emitter- coupled logic (CECL) tree and defines those stuck faults required to generate a complete DC test for the tree. The basic functional unit of a CECL circuit is a differential pair (Image Omitted) of bipolar transistors. The next higher level of CECL circuit complexity is the tree. A simple tree for computing the function f(DCBA) = (0000,0x10,100x,x11x) is shown in Fig. 1. Note that a key behavioral characteristic of a tree is that there is one and only one current path to one of its two outputs for each stimulus.

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Program for Generating a Fault MODEL of a Differential Cascode Emitter- Coupled LOGIC Tree

A program is described which defines a near minimum number of logic blocks required for a fault model of a differential cascode emitter- coupled logic (CECL) tree and defines those stuck faults required to generate a complete DC test for the tree. The basic functional unit of a CECL circuit is a differential pair

(Image Omitted)

of bipolar transistors. The next higher level of CECL circuit complexity is the tree. A simple tree for computing the function f(DCBA) = (0000,0x10,100x,x11x) is shown in Fig. 1. Note that a key behavioral characteristic of a tree is that there is one and only one current path to one of its two outputs for each stimulus. Process defects that occur in a differential pair manifest themselves as one or more of the following circuit faults: pipes (with a full range of resistance)

one emitter lead open

common emitter lead open

one base lead open

open collector lead

base-emitter short

collector-base short

(Image Omitted)

Analyses have shown that all the faults in the above list that can be detected by a DC test can be modelled by constructing a tree's fault model from a differential pair fault model. A program that finds a minimum or near minimum block count fault model for a differential CECL tree that realizes a combinational logic function is described. The faults assigned in the model are exactly the ones necessary to test all the detectable DC faults in the circuit. The algorithm can be described in terms of four major steps: 1. Make a list of all possible test patterns and the faults each covers. 2. Subsume the test patterns.

3. Select a near minimum set of test patterns using a minimization algorithm. 4. Use this test pattern set to construct the logic model and assign faults to the model. By applying the above steps, a fault model is generated for the circuit of Fig. 1. 1. LIST ALL POSSIBLE TEST PATTERNS A manual procedure for generating a test pattern for a stuck fault is to set the associated input to the value opposite the stuck value, then force the good/failing machine behavior to an output, setting other inputs as necessary. With faults stuck at 1 (sa1) and stuck at 0 (sa0) on all inputs of the circuit in Fig. 1, application of the manual procedure

1

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results in a list shown in Table 1 of all the test patterns that can be used to detect each stuck fault in the circuit of Fig. 1. 2. SUBSUME THE TEST PATTERNS Some test patterns can be subsumed by other test patterns. For example, Table 1 shows 101x as a test for device fault C3sa1 and 1010 as a test for device fault Dsa0.

However, since x is "don...