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Simultaneous Busy Channel Monitor

IP.com Disclosure Number: IPCOM000039351D
Original Publication Date: 1987-May-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 2 page(s) / 41K

Publishing Venue

IBM

Related People

Hennet, PP: AUTHOR [+3]

Abstract

The present invention is a device to measure the number of simultaneously busy channels in a computer system. It is useful to know the distribution of the number of simultaneously busy channels when designing memory and channel bus bandwidth. This information may be obtained by sampling the state of all channels (48 on the present IBM 3090 system). Each sample is a 48-bit binary vector. Counting the number of "1" bits in each sample vector produces the distribution of the number of channels that are busy at the same time. The hardware implementation of the above solution for a sampling rate of approximately 200,000 times per second is shown in the figure.

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Simultaneous Busy Channel Monitor

The present invention is a device to measure the number of simultaneously busy channels in a computer system. It is useful to know the distribution of the number of simultaneously busy channels when designing memory and channel bus bandwidth. This information may be obtained by sampling the state of all channels (48 on the present IBM 3090 system). Each sample is a 48-bit binary vector. Counting the number of "1" bits in each sample vector produces the distribution of the number of channels that are busy at the same time. The hardware implementation of the above solution for a sampling rate of approximately 200,000 times per second is shown in the figure. When the output of the "Control" binary counter equals 48 (that is, outputs labelled 16 and 32 are on), the next clock cycle (49) will load (- load) the shift register with the state of each channel where "+" = idle, "-" = busy. Also, both the A and B binary counters will be cleared at this time. The next 48 clock pulses will shift out the bits and clock them into binary counter A. When the 48th clock pulse has been completed, the output of binary counter A is latched into the D latch. The binary number represented in the D latch is strobed (on count of 48) into a decode and accumulate monitor that increments by one the value in memory address represented in the D latch (0 to 48). At the end of an interval of time, the distribution of the number of channels busy at the same time...