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Circuit for Detection of the Failure of One of Two CLOCKS

IP.com Disclosure Number: IPCOM000039354D
Original Publication Date: 1987-May-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 3 page(s) / 51K

Publishing Venue

IBM

Related People

Bersac, JM: AUTHOR [+3]

Abstract

This circuit permits the detection of the failure of one of the two clocks, assuming that only one of them may be in breakdown at any time. This device does not involve an analog technology, avoids the use of adjustable elements, and can also be checked by another circuit. This device consists of a clock generator which provides a compound clock from the two checked clocks, a detector circuit which is able to watch over the two checked clocks and a sequencer circuit which generates the functional sequence from the clock generator. This device has been particularly designed to match LSSD (Level Sensitive Scan Design) requirements. The two input frequencies, CK2 (8.00 MHz) and CK1 (4.915 MHz) have a duty cycle of 50%. After summation in the exclusive OR circuit the signal has a pseudo period between 62.

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Circuit for Detection of the Failure of One of Two CLOCKS

This circuit permits the detection of the failure of one of the two clocks, assuming that only one of them may be in breakdown at any time. This device does not involve an analog technology, avoids the use of adjustable elements, and can also be checked by another circuit. This device consists of a clock generator which provides a compound clock from the two checked clocks, a detector circuit which is able to watch over the two checked clocks and a sequencer circuit which generates the functional sequence from the clock generator.

This device has been particularly designed to match LSSD (Level Sensitive Scan Design) requirements. The two input frequencies, CK2
(8.00 MHz) and CK1 (4.915 MHz) have a duty cycle of 50%. After summation in the exclusive OR circuit the signal has a pseudo period between 62.5 ns minimum (half a period of 8.0 MHz) and 101.72 ns maximum (half a period of the 4.915 MHz). Each time the two input states change simultaneously a glitch is generated by the exclusive OR circuit. This compound CLOCK signal generated is applied at the discrete circuits of the clock generator. The first circuit is a divider by two (edge triggered) for deglitching. The second one is a two-phase generator used for the generation of the LSSD clocks. This two-phase generator divides two pseudo periods of the deglitched clock in four elementary times: 1. C CLOCK pulse. 2. Separation time between C and B CLOCKS. 3. B CLOCK pulse.
4. Separation time between B and C CLOCKS. CK1 and CK2 are divided in order to have about the same frequency (1 MHz). The 8 MHz is divided by 8, and

the 4.915 MHz is divided by 5. This is mandatory

because the input signals have a frequency greater than

the checker clock frequency. Then the two 1 MHz signals

are applied at the inputs of the clock checker circuit

itself. Each input signal is applied at a two-stage shift register latch (SRL) using t...