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Interface Circuit Between Screen Memory and Video Path to a Color Monitor

IP.com Disclosure Number: IPCOM000039355D
Original Publication Date: 1987-May-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 3 page(s) / 50K

Publishing Venue

IBM

Related People

Mansfield, RL: AUTHOR [+4]

Abstract

The circuit described below and shown in Fig. 1 functions as the interface between the screen memory and the video path to the color monitor. The circuit comprises three major parts: the first-in, first-out (FIFO) queue 10, the Look-up Table memory 11, and the Video Output stage 12. The FIFO 10 interfaces to the video memory. This FIFO accepts data from the RAMs (random-access memories) in four successive 32-bit transfers. The even and odd bits of each byte are separated, then the data is passed in a serial fashion out of FIFO 10 and into the Look-up Table. The even and odd bits follow parallel paths through the FIFO and Look-Up Table to the Video Output stage 12. By implementing the architecture in this way, FIFO 10 and Look-up Table 11 only run at half the speed of the Video Output stage 12, where the bits are recombined.

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Interface Circuit Between Screen Memory and Video Path to a Color Monitor

The circuit described below and shown in Fig. 1 functions as the interface between the screen memory and the video path to the color monitor. The circuit comprises three major parts: the first-in, first-out (FIFO) queue 10, the Look-up Table memory 11, and the Video Output stage 12. The FIFO 10 interfaces to the video memory. This FIFO accepts data from the RAMs (random-access memories) in four successive 32-bit transfers. The even and odd bits of each byte are separated, then the data is passed in a serial fashion out of FIFO 10 and into the Look-up Table. The even and odd bits follow parallel paths through the FIFO and Look-Up Table to the Video Output stage 12. By implementing the architecture in this way, FIFO 10 and Look-up Table 11 only run at half the speed of the Video Output stage 12, where the bits are recombined. The Look-up Table memory 11 uses this serial data from FIFO 10 as

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addresses to a 16-word by 6-bit/word, high speed memory. This memory enables the four independent planes of video data to be combined into 6 bits of color information to be displayed on the monitor. The Look-up Table 11 can be written into independently of any reads to it, and displayed colors can be changed without changing the information stored in the display RAM. These 6 bits of color information are then passed to the Video Output stage. Since the even and odd bits of video are

(Image Omitted)

separated, the Look-up Table RAM is equipped with two independent read ports. A block diagram of one word of the multi-ported RAM is shown in Fig. 2. As shown, this RAM has two separate read address decoders 20, 21, and data out simultaneously. In addition, a single write decoder 22 is shown. This feature allows the RAM to be written into regardless of any read cycles which may be occurring. In this application, independent write cycles are important because the memory is being read from almost continuously. Data is stored in the memory in a single storage latch, and data is enabled onto the output data bus through two sets of tri-state drivers. This data bus connects the data out of this word with the other 15 words in the memory on a common bus. The Video Output stage 12 recombines the even and odd bits into a continuous stream of video, and takes care of blanking the video during a monitor retrace. On a color all-points-addressable display system,...