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Single-Stage Emitter-Coupled Logic Gated Data Latch

IP.com Disclosure Number: IPCOM000039364D
Original Publication Date: 1987-May-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 2 page(s) / 36K

Publishing Venue

IBM

Related People

Wong, RC: AUTHOR

Abstract

This article suggests a means of implementing a gated latch with bipolar devices so that it is compatible with emitter-coupled logic (ECL) circuitry in semiconductor devices. The circuitry proposed provides a gated latch function using less silicon area and current or less voltage between the highest and lowest power supply than does presently available circuits. (Image Omitted) The proposed method suggests a means of implementing series gatings without using multiple levels of cascodes. Fig. 1 shows a gated data latch. With a low clock signal, polarity is held in the latch which consists of the J-latch, T1, T2, R1 and R2. Necessary level shiftings as well as the output drivings are provided by T7 and T8. When the clock is UP, the J-latch is diverted while J-data is switched into the latch according to the input datum.

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Single-Stage Emitter-Coupled Logic Gated Data Latch

This article suggests a means of implementing a gated latch with bipolar devices so that it is compatible with emitter-coupled logic (ECL) circuitry in semiconductor devices. The circuitry proposed provides a gated latch function using less silicon area and current or less voltage between the highest and lowest power supply than does presently available circuits.

(Image Omitted)

The proposed method suggests a means of implementing series gatings without using multiple levels of cascodes. Fig. 1 shows a gated data latch. With a low clock signal, polarity is held in the latch which consists of the J-latch, T1, T2, R1 and R2. Necessary level shiftings as well as the output drivings are provided by T7 and T8. When the clock is UP, the J-latch is diverted while J-data is switched into the latch according to the input datum. The effect of series gating is accomplished by adjusting the UP level of the clock signal swings so they are above those of the input data and the latch feedbacks. In ECL, this delta V may be accomplished with the level shift resistor R3 (Fig. 1). With the J-latch being generally well controlled, so is delta V. A two-port gated data latch is shown in Fig. 2. As in the pre ceding illustration, the clock signal UP levels must be above the UP level of the other signals. A shift register latch may then be formed by combining the circuits of Fig. 1 and Fig. 2.

(Image Omitted)

The principle proposed may...