Browse Prior Art Database

Transistor-Coupled Cts Memory Cell

IP.com Disclosure Number: IPCOM000039369D
Original Publication Date: 1987-May-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 2 page(s) / 45K

Publishing Venue

IBM

Related People

Wong, RC: AUTHOR

Abstract

A high density alternative to the Harper PNP cell has been proposed which eliminates bitline leakage. It is a transistor-coupled complementary-transistor switch (TCCTS) memory cell which is essentially a Harper PNP cell with the I/O NPN device collectors shorted to their bases. (Image Omitted) Harper PNP cells have been widely used in bipolar memory arrays since fast and dense arrays may be designed and no Schottky barrier diodes (SBD) are needed. When the cells are designed to operate in saturation, they become tightly coupled to the bit lines through read/write transistors operating in the inverse mode. The read/write transistors of the ON sides of the cells are always conducting. There are disadvantages to the foregoing couplings: 1.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 58% of the total text.

Page 1 of 2

Transistor-Coupled Cts Memory Cell

A high density alternative to the Harper PNP cell has been proposed which eliminates bitline leakage. It is a transistor-coupled complementary-transistor switch (TCCTS) memory cell which is essentially a Harper PNP cell with the I/O NPN device collectors shorted to their bases.

(Image Omitted)

Harper PNP cells have been widely used in bipolar memory arrays since fast and dense arrays may be designed and no Schottky barrier diodes (SBD) are needed. When the cells are designed to operate in saturation, they become tightly coupled to the bit lines through read/write transistors operating in the inverse mode. The read/write transistors of the ON sides of the cells are always conducting. There are disadvantages to the foregoing couplings: 1. Word line swings are retarded because of the large currents wasted to unselected cells through read/write transistors. 2. Read access is sensitive to bit patterns. 3. During standby, cell currents are mainly leakage currents. A circuit rearrangement has been proposed using the TCCTS memory cell of Fig. 1 with the bit right, BR, the bit left, BL, word line, WL, and drain line, DL, indicated. It is anticipated that this arrangement will offset the shortcomings noted above. It requires no extra process steps and with PolySi base technology, cell size remains about the same. One layout scheme of the TCCTS cell in Fig. 2 shows PolySi 1, reachthrough 2, trench isolation 3 and the emitter contact 4. Tra...