Browse Prior Art Database

Extended Series Gatings With Complementary Emitter-Coupled Logic Circuits

IP.com Disclosure Number: IPCOM000039380D
Original Publication Date: 1987-May-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 2 page(s) / 45K

Publishing Venue

IBM

Related People

Wong, RC: AUTHOR

Abstract

A method is proposed to have extended logic performed within power supply voltages in semiconductor devices. The proposal involves circuitry based upon PNP transistors. In previous work a technique allowed for infinite extension of series gatings in emitter-coupled logic circuits. This was accomplished by shifting the top voltage of a current path down to the bottom level with a PNP mirror at the top and an NPN mirror at the bottom. With such an arrangement logic is realized in the upward path by NPN switches. In this proposal it is suggested that as the voltage level is being shifted downward that PNP transistor switches also be used to perform additional logic functions along the chain of series gatings. The circuitry is shown for a 9-way NAND gate in a 3-level cascade technology. The circuitry assumes signal swings of 0.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 100% of the total text.

Page 1 of 2

Extended Series Gatings With Complementary Emitter-Coupled Logic Circuits

A method is proposed to have extended logic performed within power supply voltages in semiconductor devices. The proposal involves circuitry based upon PNP transistors. In previous work a technique allowed for infinite extension of series gatings in emitter-coupled logic circuits. This was accomplished by shifting the top voltage of a current path down to the bottom level with a PNP mirror at the top and an NPN mirror at the bottom. With such an arrangement logic is realized in the upward path by NPN switches. In this proposal it is suggested that as the voltage level is being shifted downward that PNP transistor switches also be used to perform additional logic functions along the chain of series gatings. The circuitry is shown for a 9-way NAND gate in a 3-level cascade technology. The circuitry assumes signal swings of 0.6 V; adjacent level shift of 0.6 V ( 1 Schottky barrier diode drop); and an Rx large enough so that T1 is off when VA1 = 0.8 V. T1 can be guaranteed off if Vcc and all logic levels are shifted down by about 400 mv. Transistors A and X also serve as voltage clamps. The extended series gatings are desirable in arithmetic and logic unit designs. Reference "Current Reflector in Cascode Emitter Coupled Logic," IBM Technical Disclosure Bulletin 29, 2611-2613 (November 1986).

1

Page 2 of 2

2

[This page contains 4 pictures or other non-text objects]