Browse Prior Art Database

Simplified Bus Arbitration Logic

IP.com Disclosure Number: IPCOM000039383D
Original Publication Date: 1987-Jun-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 2 page(s) / 61K

Publishing Venue

IBM

Related People

Frazier, GR: AUTHOR

Abstract

A Small Computer System Interface (SCSI) bus arbitration process includes the following steps. Any device attempting to connect to a target device must execute these steps. 1. Wait for bus-free phase. 2. Turn on BUSY signal and Initiator's identification (ID) bit. 3. If a higher priority ID bit is one, release all signals and return to 1. 4. Turn on SELECT signal and Target's ID bit. 5. Release the BUSY signal. 6. Wait for Target to reassert BUSY 7. Turn off select After these steps, a connection between the target and initiator has been established. Steps 1-3 must be accomplished in less than 2 microseconds and therefore must be implemented with hardware. For devices with the highest ID bit, however, step 3 can be skipped.

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Simplified Bus Arbitration Logic

A Small Computer System Interface (SCSI) bus arbitration process includes the following steps. Any device attempting to connect to a target device must execute these steps. 1. Wait for bus-free phase.

2. Turn on BUSY signal and Initiator's identification (ID) bit.

3. If a higher priority ID bit is one, release all signals and

return to 1.

4. Turn on SELECT signal and Target's ID bit.

5. Release the BUSY signal.

6. Wait for Target to reassert BUSY

7. Turn off select After these steps, a connection between the target and initiator has been established. Steps 1-3 must be accomplished in less than 2 microseconds and therefore must be implemented with hardware. For devices with the highest ID bit, however, step 3 can be skipped. This allows a highly simplified logic circuit to be used for steps 1 and 2, and a microprocessor can complete the remaining steps since these steps have no timing restrictions below 200 microseconds. Also, since the logic performing steps 1 and 2 is controlled by a microprocessor, all the advantages of programmable priority (e.g., allowing others to use the bus if they desire to do so at the same time as the initiator) can be retained by simply delaying a few microseconds before enabling the logic to begin step 1. This allows lower priority devices to arbitrate for the bus and obtain it before the initiator attempts to use it. The same logic can also be used to detect a reselection phase in which the target res...