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Adaptive Synchronous Data Transfer Logic

IP.com Disclosure Number: IPCOM000039385D
Original Publication Date: 1987-Jun-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 3 page(s) / 42K

Publishing Venue

IBM

Related People

Frazier, GR: AUTHOR

Abstract

An arrangement is described which allows synchronous data transfer without complex logic circuitry. "Synchronous" data transfers allow data to be transferred at high speeds over long cables by eliminating the handshake delays caused by propagation times. In a typical data transfer over a cable, "request" (REQ) pulses are sent by a controller at one end of a cable, and "acknowledge" (ACK) pulses are sent by the controller at the other end of a cable in order to synchronize data bytes flowing over the cable. The REQ-ACK signal interchange is sometimes referred to as a "handshake." In synchronous data transfers, multiple REQ pulses can be sent by one controller before it receives any ACK pulses from the other controller.

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Adaptive Synchronous Data Transfer Logic

An arrangement is described which allows synchronous data transfer without complex logic circuitry. "Synchronous" data transfers allow data to be transferred at high speeds over long cables by eliminating the handshake delays caused by propagation times. In a typical data transfer over a cable, "request" (REQ) pulses are sent by a controller at one end of a cable, and "acknowledge" (ACK) pulses are sent by the controller at the other end of a cable in order to synchronize data bytes flowing over the cable. The REQ-ACK signal interchange is sometimes referred to as a "handshake." In synchronous data transfers, multiple REQ pulses can be sent by one controller before it receives any ACK pulses from the other controller. The maximum number of unacknowledged REQ pulses which can be sent by the requesting controller is referred to as the "offset." In order to successfully complete the data transfer, however, the number of ACK pulses received by the requestor must equal the number of REQ pulses sent. In order to accomplish this with a minimum of circuitry and data buffering at the controller issuing ACK pulses, the following implementation is used. First, a small data buffer is provided; the size of the buffer must at least equal the offset value, and it must be capable of receiving data at the maximum rate at which REQ pulses may be received. A completely independent circuit can then be used to generate ACK pulses according to the following algorithm. 1. Generate buffer input/output pulses simultaneously with each

REQ pulse.

2. Generate ACK pulses at the maximum rate as log as:

(# of ACK pulses) mod N < (# of REQ pulses) mod N

-and-

The buffer is not full (during reads) or empty (during

writes). It should also be ensured that the offset value never exceeds 2N-1. This prevents the modulo N pulse counters from overflowing. Additionally, it should be ensured that the rate at which ACK pulses are generated is slightly higher than the rate at which REQ pulses are received. This allows the offset to gradually decrease after the maximum offset has been reached and the requestor has been held off by withholding ACK pulses. (This condition occurs if the buffer at the controller generating ACK pulses is full during read operations or empty during write operations.) After the offset has reached zero, the rate at which ACK pulses are generated decreases or "adapts" to the rate at which REQ pulses are received.

Fig. 1 is an example of the implementation of the above for the Case of N = 2, and an offset of 2N - 1 = 3. A two-bit wrap-ar...