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Digital Phase Comparator for Phase-Locked Loop Particularly for Varying a Computer Clock Frequency in Small Steps for Testing During Manufacturing

IP.com Disclosure Number: IPCOM000039390D
Original Publication Date: 1987-Jun-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 2 page(s) / 41K

Publishing Venue

IBM

Related People

Griess, KR: AUTHOR

Abstract

A phase-locked loop circuit comprises a variable oscillator, a source of a reference frequency, frequency dividers that receive the reference frequency and the oscillator frequency and produce a reference sub- frequency and an oscillator sub-frequency, and a digital circuit that compares the phase of the two sub-frequencies and produces an analog signal to control the oscillator phase. In one application for the circuit, the oscillator forms a variable clock for testing a computer and the reference frequency is varied in discrete steps during a test. A digital value that controls the oscillator frequency is stored in an up-down counter, and the count in the counter is applied to a digital-to-analog converter that produces a signal to vary the oscillator frequency.

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Digital Phase Comparator for Phase-Locked Loop Particularly for Varying a Computer Clock Frequency in Small Steps for Testing During Manufacturing

A phase-locked loop circuit comprises a variable oscillator, a source of a reference frequency, frequency dividers that receive the reference frequency and the oscillator frequency and produce a reference sub- frequency and an oscillator sub-frequency, and a digital circuit that compares the phase of the two sub- frequencies and produces an analog signal to control the oscillator phase. In one application for the circuit, the oscillator forms a variable clock for testing a computer and the reference frequency is varied in discrete steps during a test. A digital value that controls the oscillator frequency is stored in an up-down counter, and the count in the counter is applied to a digital-to-analog converter that produces a signal to vary the oscillator frequency. This counter is loaded with an appropriate value to begin a test, and it is counted up or counted down when the digital phase detector detects a phase error. The digital phase comparing circuit comprises two counters, one for each of the two sub- frequencies. The counters are started together and allowed to run until one counter has reached a predetermined end count. If the oscillator is in phase with the reference, the two counters will reach the end count together. The end count is high enough that the counts will differ if the frequencies differ significantly in phase. When one counter runs faster and reaches the end count first, it steps the up-down counter by 1 in the direction to bring the oscillator into phase with the reference. If the reference sub-frequency counter reaches the end count first, the up-down counter is stepped in a direction to increase the oscillator frequency. Conversely, if the oscillator sub-frequ...