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Browse Prior Art Database

High-Availability Floating-Point Option

IP.com Disclosure Number: IPCOM000039406D
Original Publication Date: 1987-Jun-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 2 page(s) / 52K

Publishing Venue

IBM

Related People

Bechdel, JF: AUTHOR [+3]

Abstract

A floating-point unit (FPU) consisting of two identical floating-point processors and a system bus adapter uses two processors to improve error detection. This provides a means of continuing system operation, without performance degradation, after a fault is encountered in the FPU by disabling one of the processors and continuing with the remaining processor. The FPU consists of a system bus adapter and two floating-point (Image Omitted) processors in a master/slave configuration. The adapter sends identical commands and data to the processors, then compares their results as they are returned through the adapter to the Instruction Processing Unit (IPU).

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High-Availability Floating-Point Option

A floating-point unit (FPU) consisting of two identical floating-point processors and a system bus adapter uses two processors to improve error detection. This provides a means of continuing system operation, without performance degradation, after a fault is encountered in the FPU by disabling one of the processors and continuing with the remaining processor. The FPU consists of a system bus adapter and two floating-point

(Image Omitted)

processors in a master/slave configuration. The adapter sends identical commands and data to the processors, then compares their results as they are returned through the adapter to the Instruction Processing Unit (IPU). In order to implement the high-availability floating-point option, the adapter was designed with the capability to reconfigure its internal data flow and disable either of the floating-point processors. Fig. 1 is a high-level depiction of the data flow within the system bus adapter. In a normally-operating system, the results of floating- point operations are latched first from the master floating-point processor into FREG1, then from the slave into FREG2. If the results are equal, then the data in FREG1 is sent to the IPU over the D-bus. In the event of a miscompare, a machine check occurs and the system is halted. At this point, the floating-point option is invoked by first running a diagnostic program to determine which floating-point processor is in error. The service pr...