Browse Prior Art Database

New Latch Family for Mesfet Gate Arrays in DCFL Logic

IP.com Disclosure Number: IPCOM000039412D
Original Publication Date: 1987-Jun-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 3 page(s) / 61K

Publishing Venue

IBM

Related People

Boudon, G: AUTHOR [+4]

Abstract

Latches represent a large portion of the silicon area in logic chips. It is especially true for DCFL gate arrays where latches require a large number of devices. Fig. 1 shows the schematic of a shift register latch which uses 44 devices when built with conventional NOR gates (12 NOR 2 way plus 5 inverters). This scheme has two disadvantages which are in contradiction with the objective - speed - and present capabilities - yield - of the GaAs technology: long delay path and large number of devices. It is therefore essential to design new schemes with shorter delay paths and fewer devices. This proposal achieves these two objectives. The circuit disclosed hereafter (see Fig. 2) is compatible with a GaAs gate array with enhancement/depletion devices. All the devices of the same type have the same size.

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New Latch Family for Mesfet Gate Arrays in DCFL Logic

Latches represent a large portion of the silicon area in logic chips. It is especially true for DCFL gate arrays where latches require a large number of devices. Fig. 1 shows the schematic of a shift register latch which uses 44 devices when built with conventional NOR gates (12 NOR 2 way plus 5 inverters). This scheme has two disadvantages which are in contradiction with the objective - speed - and present capabilities - yield - of the GaAs technology: long delay path and large number of devices. It is therefore essential to design new schemes with shorter delay paths and fewer devices. This proposal achieves these two objectives. The circuit disclosed hereafter (see Fig. 2) is compatible with a GaAs gate array with enhancement/depletion devices. All the devices of the same type have the same size. The shift register is composed of a master latch L1 which drives a slave latch L2 through a gating circuit G2. The gating circuit G2 is controlled by the regular B0 clock required in any LSSD implementation. Several inputs can be multiplexed into the master latch by gating the circuits G1A, G1B, etc., connected to the L1 outputs in a DOT function (nodes PL1 and ML1). The two latches are based on the concept of cross-

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coupled inverters made of enhancement devices T2 and T4 loaded by depletion devices T1 and T3. Clocks A0, B0 and C0 are normally at down level; the latches are totally separated form each other and from the input levels by the gating circuits since the transistors T9, T14 and T17 are switched off by the down levels applied to their gates. The latches are...