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Global Area Planner for Very Large-Scale Integration Custom or Semi-Custom Chips

IP.com Disclosure Number: IPCOM000039430D
Original Publication Date: 1987-Jun-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 3 page(s) / 58K

Publishing Venue

IBM

Related People

Patel, PT: AUTHOR [+2]

Abstract

In very large custom or semi-custom chips, it is important to determine the actual area required for global wiring for optimum chip size. A method is described which is employed for accurate global area sizing. For large custom or semi-custom designs, there is no method available which will calculate the area required for global wiring. There might be some floor planning tools which can assist in approximate sizing. However, these tools are not integrated with the design cycle, and the solutions obtained by two different algorithms (planning and design) are never the same. Hence, until the chip is designed, the area allocated for global wiring is never certain. (Image Omitted) There are three steps for the area planner method: 1. Tiling of the chip into pieces called wire regions. 2.

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Global Area Planner for Very Large-Scale Integration Custom or Semi- Custom Chips

In very large custom or semi-custom chips, it is important to determine the actual area required for global wiring for optimum chip size. A method is described which is employed for accurate global area sizing. For large custom or semi-custom designs, there is no method available which will calculate the area required for global wiring. There might be some floor planning tools which can assist in approximate sizing. However, these tools are not integrated with the design cycle, and the solutions obtained by two different algorithms (planning and design) are never the same. Hence, until the chip is designed, the area allocated for global wiring is never certain.

(Image Omitted)

There are three steps for the area planner method:

1. Tiling of the chip into pieces called wire regions.

2. Routing global nets through wire regions.

3. Evaluating traffic congestion in each wire region.

1. Tiling Of The Chip The space on the chip which is not used by any of the macros is divided into several wire regions. Boundaries of each wire

region are defined by extending horizontal and vertical edges

of each macro until they meet another macro or prime cell

boundary. Thus, unused space is divided into several

rectangles. Each of these rectangles are considered wire

regions. An example is shown in Fig. 1 where blocks 1 through

35 are wire regions.

2. Routing Of Global Nets

Routing of global nets can be done using an interactive

graphic router or with an auto router. The best approach for

any method is to use constellations. This approach reduces

complexity of the wiring problem significantly such that,

routing constellations interactively using graphics becomes

easy, and it does not require the sophisticated auto router.

As a constellation is being routed through wire regions, the

path is being stored under the appropriate record of each wire

region.

If the constellation is pass...