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Browse Prior Art Database

Personalization of Multiple Address Categories

IP.com Disclosure Number: IPCOM000039435D
Original Publication Date: 1987-Jun-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 2 page(s) / 50K

Publishing Venue

IBM

Related People

Aichelmann, FJ: AUTHOR

Abstract

A personalization structure is described for multiple defective categories in memory arrays which results in a common type for each category. The method adds logic to a semiconductor chip to provide address personalization. This results in a common part number within each partial-good category, i.e., half-good, quarter-good, etc. (Image Omitted) In semiconductor manufacturing methods partial-good products have been used as a means of increasing memory array productivity. Use of such products can require the user to provide special wiring and selection logic in order to facilitate the use of all part numbers within a given category. This is not the case with an all-good product. The proposed personalization technique provides a means of developing a common part for each category (i.e.

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Personalization of Multiple Address Categories

A personalization structure is described for multiple defective categories in memory arrays which results in a common type for each category. The method adds logic to a semiconductor chip to provide address personalization. This results in a common part number within each partial-good category, i.e., half- good, quarter-good, etc.

(Image Omitted)

In semiconductor manufacturing methods partial-good products have been used as a means of increasing memory array productivity. Use of such products can require the user to provide special wiring and selection logic in order to facilitate the use of all part numbers within a given category. This is not the case with an all-good product. The proposed personalization technique provides a means of developing a common part for each category (i.e., halves) and also details a structure suitable for multiple categories. The incorporation of additional on-chip personalization logic is the key to the development, with the personalization done during the chip-testing activity. The block diagram of a memory chip 1 (Fig. 1) with personalization logic 2 has the address input 3 pass through the logic into the decoder 4 as well as directly to the decoder. Memory array cells 5 and an I/O interface 6 are used for the exchange of data (7). The structure for address personalization for multiple categories is given in Fig. 2. This includes an example 8 of how a fusible link 9 may be used for th...