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Browse Prior Art Database

Simple Bifet

IP.com Disclosure Number: IPCOM000039437D
Original Publication Date: 1987-Jun-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 2 page(s) / 47K

Publishing Venue

IBM

Related People

Malaviya, SD: AUTHOR

Abstract

The semiconductor process produces a compact, symmetrical NPN transistor plus a P-base resistor ready for first-level metal using only four masks. By using four additional masks in a modification to the process, a submicron-channel, field-effect transistor (FET) with a lightly-doped drain can be included in the structure. The basic structure of the NPN transistor is shown in idealized form in Fig. 1, where the N+ substrate 1 is processed to form a stud- shaped structure. P+ region 26 forms the base with N+ regions 25 and 27 forming the emitter and collector of the transistor. Metal regions 28 and 29 serve as connections to the emitter and collector. Regions 23 and 24 are insulating layers. The structure for the FET (not shown in Fig. 1) is very similar physically to that of Fig.

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Simple Bifet

The semiconductor process produces a compact, symmetrical NPN transistor plus a P-base resistor ready for first-level metal using only four masks. By using four additional masks in a modification to the process, a submicron-channel, field-effect transistor (FET) with a lightly-doped drain can be included in the structure. The basic structure of the NPN transistor is shown in idealized form in Fig. 1, where the N+ substrate 1 is processed to form a stud- shaped structure. P+ region 26 forms the base with N+ regions 25 and 27 forming the emitter and collector of the transistor. Metal regions 28 and 29 serve as connections to the emitter and collector. Regions 23 and 24 are insulating layers. The structure for the FET (not shown in Fig. 1) is very similar physically to that of Fig. 1 but has the addition of a gate oxide layer and polysilicon (poly) gate electrode processed into the upper section of region 26. In the FET structure, region 25 serves as a drain and region 27 as a source. The process produces both the NPN transistor and the FET although it can be simplified to produce just the NPN transistor. Fig. 2 illustrates the result of the process wherein this structure includes: the starting silicon substrate 1; N+ collector 2; silicon dioxide layer 12; silicon nitride layer 13; silicon dioxide layer 16; platinum silicide layer 17; insulator layer 18 of silicon dioxide or silicon nitride; planar insulator layer 19 of polyimide, quartz etc.; metal layer 20 of, for example, Al-Cu; and planar insulator 21 of polyimide, quartz, etc. The process used to a...