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Increasing Memory Reliability Through Address Translation and Per Page Bit Swapping

IP.com Disclosure Number: IPCOM000039445D
Original Publication Date: 1987-Jun-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 4 page(s) / 41K

Publishing Venue

IBM

Related People

Kuhlman, CL: AUTHOR [+2]

Abstract

Use of high density dynamic RAM in computer systems and subsystems increases the likelihood of a failure in the system or subsystem unless additional circuitry is provided to mask the failures within the dynamic RAM. This does not prevent failures of the dynamic RAM but prevents the failure from being propagated to other parts of the system or subsystem. The failure modes of a dynamic RAM are Module failures. ROW failures. COLUMN failures. Combination ROW and COLUMN failures. SOFT ERRORS. The soft errors have been handled adequately with error correction codes (ECCs) and memory scrubbing algorithms. Module failures have, in the past, been handled by swapping in a spare memory module for the failing module.

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Increasing Memory Reliability Through Address Translation and Per Page Bit Swapping

Use of high density dynamic RAM in computer systems and subsystems increases the likelihood of a failure in the system or subsystem unless additional circuitry is provided to mask the failures within the dynamic RAM. This does not prevent failures of the dynamic RAM but prevents the failure from being propagated to other parts of the system or subsystem. The failure modes of a dynamic RAM are Module failures.

ROW failures.

COLUMN failures.

Combination ROW and COLUMN failures.

SOFT ERRORS. The soft errors have been handled adequately with error correction codes (ECCs) and memory scrubbing algorithms. Module failures have, in the past, been handled by swapping in a spare memory module for the failing module. This, however, may cause other errors to occur within the memory array address space if the spare module is not entirely clear of failures. Often these failures can be handled by the software during allocation of data buffers by not allocating portions of the array address space with failures. More times than not, however, there is a kernel of code, usually the operating system and interrupt handling code, which may not reside in a portion of memory which contains failures and cannot be allocated a different array address space. This problem can be overcome by translation of memory ranges within the hardware and per page bit swapping. This will also inherently mask ROW failures of the dynamic RAM if the translation segments are on a ROW boundary. It should also be noted that the COLUMN failures can also be masked if a second translation is provided on a column basis. Translation of memory ranges will provide a failure-free portion of memory for critical code to reside. Per page bit swapping will mask ROW failures of the dynamic RAM array. The concept may be expanded to include the COLUMN failures if the extra cost is justified for the application. The availability of very fast static RAMS, as the type used for cache memory, make it possible to translate the memory ranges of a dynamic RAM array in real time. Fig. 1 shows the basic concept. Typically, when the processor or a device attached to the processor bus accesses the dynamic RAM, the memory controller multiplexes the address into a high address and a low address and presents them to the dynamic RAM as a ROW address and a COLUMN address. In order to translate the memory on a ROW basis, the high-order address bits normally sent to the dynamic RAM as the Row address is intercepted by the memory controller and presented to the fast static RAM as an address for a translation access. The data returned contains the new high- order address bits for the particular block of addresses. The memory controller presents this new address to the dynamic RAM as the ROW address. Likewise, although not shown, the low-order address bits could be translated for a new COLUMN address. The fast static RAM must be in...