Browse Prior Art Database

Memory Tester

IP.com Disclosure Number: IPCOM000039446D
Original Publication Date: 1987-Jun-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 2 page(s) / 59K

Publishing Venue

IBM

Related People

Puri, PP: AUTHOR [+2]

Abstract

Memory circuit testers are typically special-purpose tester devices which are connected to a general purpose computer as the source of test patterns for carrying out testing operations. The general-purpose computer will load blocks of test pattern words, typically 1,024 words per block, into a local tester memory of the tester. The tester will then sequentially access each of the test pattern words from the local tester memory and will output each consecutive test pattern to a device under test. A problem arises in the excessive time required to load the local tester memory with the blocks of test pattern words from the general- purpose computer.

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Memory Tester

Memory circuit testers are typically special-purpose tester devices which are connected to a general purpose computer as the source of test patterns for carrying out testing operations. The general-purpose computer will load blocks of test pattern words, typically 1,024 words per block, into a local tester memory of the tester. The tester will then sequentially access each of the test pattern words from the local tester memory and will output each consecutive test pattern to a device under test. A problem arises in the excessive time required to load the local tester memory with the blocks of test pattern words from the general- purpose computer. The slower host computer's memory and the handshaking protocol necessary to convey each consecutive block of test pattern words to the tester makes the lengthy testing of large array memory products prohibitive. Generally, the testing of a large array memory product involves the repetition of similar test patterns which vary from one another by one or two bits, for example when a particular test data input pattern is to be consecutively applied to sequentially incremented addresses for the memory device under test. The invention disclosed herein provides both a method and hardware modification to existing memory testers to enable less frequent reloading of the local tester memory from the host computer while maintaining a large repertoire of effective test pattern words, so as to enable the thorough testing of large array memory products without suffering the excessive reload time which would otherwise be necessary to convey a large number of consecutive blocks of test pattern words from the host computer to the local tester memory. As shown in the figure, a local tester memory 1 has 2m test pattern word storage locations (typically 1,024), each of the test pattern words being N bits each (typically 60 bits). In this application, at least one of the outputs from the local tester memory must remain unuse...