Browse Prior Art Database

Pipeline Prefetch Detector

IP.com Disclosure Number: IPCOM000039452D
Original Publication Date: 1987-Jun-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 2 page(s) / 51K

Publishing Venue

IBM

Related People

Kurple, KG: AUTHOR

Abstract

Many high speed processors have a pipelined architecture where macro instructions are prefetched to avoid long memory fetch times after an instruction is executed. In one microprocessor, for example, the pipeline contains the next two sequential macro instructions or data words ahead of the current instruction being executed. A problem which arises when using a pipelined architecture is that during the execution of a store instruction the possibility exists that the data could be stored into a memory location which has already been loaded into the pipe. If a circuit is not provided to detect this condition, then the pipe must be reloaded every time a store instruction is executed. Depending upon how often store instructions are executed this could have a major impact on performance.

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Pipeline Prefetch Detector

Many high speed processors have a pipelined architecture where macro instructions are prefetched to avoid long memory fetch times after an instruction is executed. In one microprocessor, for example, the pipeline contains the next two sequential macro instructions or data words ahead of the current instruction being executed. A problem which arises when using a pipelined architecture is that during the execution of a store instruction the possibility exists that the data could be stored into a memory location which has already been loaded into the pipe. If a circuit is not provided to detect this condition, then the pipe must be reloaded every time a store instruction is executed. Depending upon how often store instructions are executed this could have a major impact on performance. Therefore, a general Boolean expression is disclosed herein to detect this condition. The general Boolean equation is shown in Table 1. The expression determines whether the difference between the program counter and the memory address is equal to one or two, which would be the case if the data is being stored into a memory location which has already been loaded into the pipe. There are numerous ways in which to design a circuit embodying this expression to detect whether the difference between the two numbers is one or two. One example is the circuit shown in the figure where a three bit slice is depicted. If the binary value of the program counter (P) and...