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Address Translation Register Buffering for Processor

IP.com Disclosure Number: IPCOM000039458D
Original Publication Date: 1987-Jun-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 2 page(s) / 42K

Publishing Venue

IBM

Related People

Dahl, SS: AUTHOR [+4]

Abstract

The buffering includes registers 20-28, concatenate logic 29 and OR circuitry 30 connecting an ATR (address translation registers) stack 31 with a real address line 32. The performance of a certain processor or computer is bound by the speed of the interface to the memory of the processor. Related to this boundary is the speed at which the main store addresses can be generated. In this processor, the ATR existed on a separate chip, and whenever an address was to be generated, the correct ATR had to be fetched from the register chip. With slow system clocks, this access time can be overlapped with other processor functions, but if the access time is much slower than the system clock speed, this expedient is not possible.

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Address Translation Register Buffering for Processor

The buffering includes registers 20-28, concatenate logic 29 and OR circuitry 30 connecting an ATR (address translation registers) stack 31 with a real address line 32. The performance of a certain processor or computer is bound by the speed of the interface to the memory of the processor. Related to this boundary is the speed at which the main store addresses can be generated. In this processor, the ATR existed on a separate chip, and whenever an address was to be generated, the correct ATR had to be fetched from the register chip. With slow system clocks, this access time can be overlapped with other processor functions, but if the access time is much slower than the system clock speed, this expedient is not possible. Therefore, in order to maintain the increase in performance associated with the increase in clock speed, the buffering hereof provides a faster way of address generation (or faster ATR fetching). The buffer is composed in particular of the three data buffers 20, 21 and 22 with associated keys in registers 23, 24 and 25. Each data buffer is paired with a machine cycle type, namely, one of the three machine cycle types: IFETCH, OPERAND1. and OPERAND2. The addresses in registers 33, 34 and 35 corresponding to OP1, OP2 and IAR (instruction address register) are obtained from the memory of the processor, and the ATR stack 31 is contained in that memory. During address generation, the machine cycle type is used to select the data from one of the buffers 20, 21 and 22. The data is selected regardless of whether the key (in one of registers 26, 27 and 28) compares and is used directly to generate that address. In parallel, the key information in the latter registers is selected and compared by means of compare units 36, 37 or 38...