Browse Prior Art Database

NAND Decoder and Latch for Static RAM Decoder

IP.com Disclosure Number: IPCOM000039461D
Original Publication Date: 1987-Jun-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 2 page(s) / 49K

Publishing Venue

IBM

Related People

Kroesen, PL: AUTHOR [+3]

Abstract

A low-power, high-speed decoder has been designed for a clocked field- effect transistor (FET) static random-access memory (RAM). The concept is based on an NAND configuration as opposed to the conventional NOR circuit and is applicable to N-type metal oxide semiconductors (NMOS). For large static RAMs the decoder power dissipation is the major contributor to the total RAM active as well as standby power consumption. As the speed and size of the RAMs increase, the slow speed of the decoder and its power consumption become significant drawbacks. (Image Omitted) An improved decoder circuit (Fig. 1) functions at low power and high speed and is based on the NAND configuration. With the conventional NOR circuit, all of the decoders, except the selected one, are drawing current and dissipating power.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 53% of the total text.

Page 1 of 2

NAND Decoder and Latch for Static RAM Decoder

A low-power, high-speed decoder has been designed for a clocked field- effect transistor (FET) static random-access memory (RAM). The concept is based on an NAND configuration as opposed to the conventional NOR circuit and is applicable to N-type metal oxide semiconductors (NMOS). For large static RAMs the decoder power dissipation is the major contributor to the total RAM active as well as standby power consumption. As the speed and size of the RAMs increase, the slow speed of the decoder and its power consumption become significant drawbacks.

(Image Omitted)

An improved decoder circuit (Fig. 1) functions at low power and high speed and is based on the NAND configuration. With the conventional NOR circuit, all of the decoders, except the selected one, are drawing current and dissipating power. Only the the selected decoder consumes power in the NAND configuration. In other designs using the NAND configuration it has been difficult to guarantee a true down level at the top node of the stack of input series devices. The proposed circuit of Fig. 1 avoids that problem by using a differential configuration so the only requirement is a difference in voltage from the selected node (node 5) to the node on the other side of the latch (node 6). The CSB signal precharges node 6 and the decoder transfer gate to VDD-VT. CSB also holds node 5 and the NAND gate voltage well above VDD-VT, the reference level. During the active cycle of the circuit, node 5 will quickly follow CSB down for the selected decoder. Node 5 of the unselected decoders will remain at the original high voltage because at least one of the stacked pull-down devices is off. A small pull-up device (T9) on node 5 will assu...