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Browse Prior Art Database

Multiplier-Accumulate Architecture

IP.com Disclosure Number: IPCOM000039466D
Original Publication Date: 1987-Jun-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 3 page(s) / 53K

Publishing Venue

IBM

Related People

Mercy, BR: AUTHOR [+2]

Abstract

A multiplier-accumulate architecture is disclosed which is capable of being embodied on a single integrated circuit chip. Several integrated circuit chips with this architecture can be interconnected so that complex arithmetic operations can be performed, such as finite impulse response filtering and other digital signal processing operations. In the invention disclosed herein, a basic processing kernel architecture is shown in Fig. 1 which is embodied on a single integrated circuit chip, allowing a multiplicity of such single-chip processors to be interconnected in a time divided network for performing identical arithmetic operations in parallel on an input data stream, the results of which are merged on a time divided basis as filtered output data. The circuit of Fig.

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Multiplier-Accumulate Architecture

A multiplier-accumulate architecture is disclosed which is capable of being embodied on a single integrated circuit chip. Several integrated circuit chips with this architecture can be interconnected so that complex arithmetic operations can be performed, such as finite impulse response filtering and other digital signal processing operations. In the invention disclosed herein, a basic processing kernel architecture is shown in Fig. 1 which is embodied on a single integrated circuit chip, allowing a multiplicity of such single-chip processors to be interconnected in a time divided network for performing identical arithmetic operations in parallel on an input data stream, the results of which are merged on a time divided basis as filtered output data. The circuit of Fig. 1 has its basis of operation in applying selected path delays to several paths for the data through the circuit so that later arriving data at the input to the circuit will arrive simultaneously at the output with earlier arriving data to the circuit. The path elements in the circuit of Fig. 1 are numbered from one through 15. Path 1 is through the elements 1, 2, 3 and 4. Path 2 is through the elements 1, 6, 7, 8, 9 and 10. Path 3 is through elements 1, 11, 12, 7, 8, 9 and 10. Path 4 is through elements 1, 11, 13, 14, 15, 3 and 4. In this illustration, four sequential operands are input to the circuit on line 1. The operands can be labeled 01, 02, 03 and 04, with their subscripts indicating the time of arrival of the operand at the input. It is an object of the invention to get the results of the arithmetic operations on operands 01, 02, 03 and 04 to arrive at the addend input and augend input of the adder 5 at the same time. In the circuit of Fig. 1, path 1 is shorter than path 2, which is shorter than path 3, which is shorter than path 4. Each of the operands 01 through 04 travels all of the paths. However, initially, the only meaningful path for the operand 01 is over path 4, the longest path. Initially, the only meaningful operand for 02 is along path 3, the second longest path. Initially, the only meaningful path for the operand 03 is along p...