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Improved Silicide Sub-Micron Fet Structure

IP.com Disclosure Number: IPCOM000039467D
Original Publication Date: 1987-Jun-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 2 page(s) / 53K

Publishing Venue

IBM

Related People

Gera, JS: AUTHOR [+2]

Abstract

This article describes a reliable process for forming low resistance sub-micron polysilicon conductors while decreasing RIE (reactive ion etch) process uncertainties and bridging phenomena effects characteristic of the conventional processes. (Image Omitted) Fig. 1 illustrates in a cross-sectional view a conventional sidewall image transfer (SIT) process. Following completion of the SIT process, a sub-micron polysilicon line (gate) remains, as shown in Fig. 2. A layer of low temperature oxide (LTO) remains on top of the polysilicon line following completion of the polysilicon RIE process. Fig. 3 illustrates a further step in the process wherein an oxide is deposited over the line structure shown in Fig. 2.

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Improved Silicide Sub-Micron Fet Structure

This article describes a reliable process for forming low resistance sub-micron polysilicon conductors while decreasing RIE (reactive ion etch) process uncertainties and bridging phenomena effects characteristic of the conventional processes.

(Image Omitted)

Fig. 1 illustrates in a cross-sectional view a conventional sidewall image transfer (SIT) process. Following completion of the SIT process, a sub-micron polysilicon line (gate) remains, as shown in Fig. 2. A layer of low temperature oxide (LTO) remains on top of the polysilicon line following completion of the polysilicon RIE process. Fig. 3 illustrates a further step in the process wherein an oxide is deposited over the line structure shown in Fig. 2. An oxide RIE is then completed in order to form oxide spacers which are employed as ion-implant block-outs for source and drain areas lying next to the polysilicon line. The success of the following process steps depends upon the complete removal of all oxide remaining on top of the polysilicon line in order that the silicide formation thereon be optimized. To this end, an over-etch (O.E.) is performed. The absence of information regarding the thickness of the oxide layer creates a problem at this stage of processing, however. Insufficient O.E. may result in inadequate silicide formation. Excessive O.E. may result in an inadequate recessed oxide isolation (ROI) region, or in the worst case, no ROI. Additionally, due to...