Browse Prior Art Database

Page Image Pipeline

IP.com Disclosure Number: IPCOM000039480D
Original Publication Date: 1987-Jun-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 2 page(s) / 23K

Publishing Venue

IBM

Related People

Bantz, DF: AUTHOR [+3]

Abstract

Bitmaps containing graphic data for very high speed printers can be rapidly created by pipelining the computation. In this approach each set of update logic has a separate random- access memory (RAM) and writes the pixels of graphic objects into that RAM within one interval. At the end of that interval, the contents of the RAM are transferred to the next station in the pipeline where the next set of update logic will add more pixels. In the final stage, the RAM is drained to the print engine, typically a high-speed serial printhead. The RAMs in each stage are made with so-called "video DRAMs", which are chips with a shift register capable of shifting data in and out at high speeds.

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Page Image Pipeline

Bitmaps containing graphic data for very high speed printers can be rapidly created by pipelining the computation. In this approach each set of update logic has a separate random- access memory (RAM) and writes the pixels of graphic objects into that RAM within one interval. At the end of that interval, the contents of the RAM are transferred to the next station in the pipeline where the next set of update logic will add more pixels. In the final stage, the RAM is drained to the print engine, typically a high-speed serial printhead. The RAMs in each stage are made with so-called "video DRAMs", which are chips with a shift register capable of shifting data in and out at high speeds. For example, if each RAM were made with 256K by 4 video DRAMs capable of shifting at 25MHz, the time to copy the contents of one stage to the next would be about 10 milliseconds, less than 10% of the time available in a stage. Below is pictured such a system: Each stage, represented by Update Logic (UL) and its associated RAM, gets some portion of the work from the coded graphic store. During an interval, it writes pixels into its RAM. At the end of the interval, the contents of all RAMs are copied one stage to the right. Note that any stage could have more than one UL- RAM set: data from the RAM to the left would be copied into all RAMs of a stage, and data from all RAMs in a stage would be merged together to be copied to the RAM to the right. This replication with...