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General-Purpose Interface Receiver for CMOS Technology

IP.com Disclosure Number: IPCOM000039481D
Original Publication Date: 1987-Jun-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 2 page(s) / 43K

Publishing Venue

IBM

Related People

Swart, DP: AUTHOR

Abstract

This CMOS Off-Chip receiver is capable of receiving low-level logic signals, where the Up-Level voltage is as low as 1.5 V. Standard TTL (transistor-transistor logic) receivers do not respond reliably to this Up-Level voltage. The TTL input transistor is configured to have high voltage gain, such that the output responds to the low-level input signal with minimum delay time. Input stage 1 is connected as a common gate transistor. When the input voltage 20 is at a Down-Level, transistor 1 conducts current from node 21 to node 20. This current discharges node 21 until its voltage is approximately equal to input voltage 20. This voltage at node 21 then turns P channel FET transistor 3 ON and N channel FET transistor 4 OFF, resulting in an Up-Level output voltage at output 22.

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General-Purpose Interface Receiver for CMOS Technology

This CMOS Off-Chip receiver is capable of receiving low-level logic signals, where the Up-Level voltage is as low as 1.5 V. Standard TTL (transistor- transistor logic) receivers do not respond reliably to this Up-Level voltage. The TTL input transistor is configured to have high voltage gain, such that the output responds to the low-level input signal with minimum delay time. Input stage 1 is connected as a common gate transistor. When the input voltage 20 is at a Down- Level, transistor 1 conducts current from node 21 to node 20. This current discharges node 21 until its voltage is approximately equal to input voltage 20. This voltage at node 21 then turns P channel FET transistor 3 ON and N channel FET transistor 4 OFF, resulting in an Up-Level output voltage at output 22. When an Up-Level voltage is applied to input 20, transistor 1 is turned OFF because its gate-to-source voltage is too low for it to conduct. Then transistor 2 charges node 21 up to supply voltage VDD (positive power supply). As a result, transistor 3 is turned OFF, transistor 4 is turned ON, and output node 22 is pulled to a Down- Level of 0.0 volts.

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The reference voltage at node 23 is critical to the operation of this circuit. It should be equal to the SWITCHING THRESHOLD plus the threshold voltage of transistor 1. The length and width of transistors 5, 6, 7 and 8 should preferably be chosen such that this will be quite a...