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RESYNCHRONIZATION PROCEDURE OF A LINK

IP.com Disclosure Number: IPCOM000039483D
Original Publication Date: 1987-Jun-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 3 page(s) / 51K

Publishing Venue

IBM

Related People

Bonnet, R: AUTHOR [+4]

Abstract

This article relates to a method for recovering the synchronism of the receiving side of a link with the remote transmitting side after a perturbation in the transmission. It is assumed that the frame has the configuration described in European Patent Application No. 85450266. The link is a full duplex link. For each direction, the receive side must stay synchronized with the remote transmit side to be able to understand the contents of the frame which transports circuit-switched and packet-switched bits. For a given link speed, the medium frame is nearly constant in duration.

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RESYNCHRONIZATION PROCEDURE OF A LINK

This article relates to a method for recovering the synchronism of the receiving side of a link with the remote transmitting side after a perturbation in the transmission. It is assumed that the frame has the configuration described in European Patent Application No. 85450266. The link is a full duplex link. For each direction, the receive side must stay synchronized with the remote transmit side to be able to understand the contents of the frame which transports circuit-switched and packet-switched bits. For a given link speed, the medium frame is nearly constant in duration. The medium frame duration is: Nc x BT < n x T < (Nc+1) x BT _ where BT is the bit time, Nc the number of bits of the frame,

n the number of subframes comprised in the frames, and

T is the conventional time multiplex slot duration which is

generally equal to 125 microseconds. The number of bits per frame is not constant but may vary by 1. The synchronization of the receive side is made by counting the number of bits in an Nc counter. If Nc is equal to X bits, as it is not known whether X is the high value Nc+1 or the low value Nc, the next frame may contains either X bits, X-1 bits or X+1 bits. The synchronization is performed by observing the recurrence of the ending flag within these limits of +1 or -1 bit. To control the synchronization of the link, the XMIT component issues a flag at the 125 microseconds clock transition which follows the transmission of Nc bits. The receive side comprises an Nc counter, initialized at each end of flag time, incremented at each bit time, which holds the number of received bits of a frame, and a Nc register which holds the number of bits of the previous frame and thus represents the supposed number of bits of the present frame. (The clocks have a good accuracy so that the number of bits in a frame does not change very often.) When the contents of the Nc counter and the Nc register are equal, the RCV component verifies where the beginning of a flag is. The flag is detected by its first 3 bits (O 1 1) used for synchronization, the other 5 bits being used for control of the frame on some occasions, i.e., to modify the frame format. To check where the beginning of the flag is, the following logic is used: The received frame enters a shift register which holds 10 bits. It is compared at supposed flag time (Nc bits received) with a register that...