Browse Prior Art Database

Determination of the Link Parameters to Be Used in a Mechanism for Transporting Circuit-Switched Bits and Packet-Switched Bits

IP.com Disclosure Number: IPCOM000039484D
Original Publication Date: 1987-Jun-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 2 page(s) / 63K

Publishing Venue

IBM

Related People

Bonnet, R: AUTHOR [+4]

Abstract

The proposed method is to be used in a mechanism, such as described in European Patent Application No. 854500266, wherein the data on the links of the telecommunication network are sent in frames beginning with a framing medium flag MF and comprising n subframes. Each subframe comprises Ns bits and some padding bits of the packet type which are added to form a frame of Nc bits. The link parameters n, Nc and Ns depend upon the transmission speed of the link. Fig. 1 shows the configuration of the frames and subframes. For each link, a master clock, which is the image of the link speed, a T-Clock with T=125 microsecond in the preferred embodiment, and the medium flag rate, which is a maximum of one MF per 256 bits, are provided to the circuit shown in Fig. 2, which is located at the transmit side of the link.

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Determination of the Link Parameters to Be Used in a Mechanism for Transporting Circuit-Switched Bits and Packet-Switched Bits

The proposed method is to be used in a mechanism, such as described in European Patent Application No. 854500266, wherein the data on the links of the telecommunication network are sent in frames beginning with a framing medium flag MF and comprising n subframes. Each subframe comprises Ns bits and some padding bits of the packet type which are added to form a frame of Nc bits. The link parameters n, Nc and Ns depend upon the transmission speed of the link. Fig. 1 shows the configuration of the frames and subframes. For each link, a master clock, which is the image of the link speed, a T-Clock with T=125 microsecond in the preferred embodiment, and the medium flag rate, which is a maximum of one MF per 256 bits, are provided to the circuit shown in Fig. 2, which is located at the transmit side of the link. The frame parameters are determined differently at the transmit and receive sides of the link. At the transmit side, a first counter CTR1 counts the number of T-signal transitions and saves it into clock register REG1. A second counter CTR2 counts the number of master clock transitions and, at each T-signal transition, this count is saved into the master clock register REG2. The count enable signal provided by latch LTH causes the counters CTR1 and CTR2 to be reset and started. When counter CTR2 reaches 256, counters CTR1 and CTR2 are s...