Browse Prior Art Database

Synchronization Process of a Link

IP.com Disclosure Number: IPCOM000039486D
Original Publication Date: 1987-Jun-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 3 page(s) / 39K

Publishing Venue

IBM

Related People

Bonnet, R: AUTHOR [+4]

Abstract

The logic represented in the drawing is used to verify that the receive side of a link stays in synchronism with the remote transmit side. The link is a full duplex link. For each direction, the receive side must stay synchronized with the remote transmit side to be able to understand the contents of the frame flowing in each direction, which is a mixture of circuit and packet traffic. It is assumed that the frames have the configuration described in European Patent Application No. 854500266. By definition and for a given line speed, the medium frame is nearly constant in duration. The medium frame duration is: Nc x BT < NF * 125 microsec < (Nc+1) x BT _ where Nc is the number of bits in the frame, and BT is the bit time. As a consequence, the number of bits per frame is equal to a constant Nc+0 or +1 bit.

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Synchronization Process of a Link

The logic represented in the drawing is used to verify that the receive side of a link stays in synchronism with the remote transmit side. The link is a full duplex link. For each direction, the receive side must stay synchronized with the remote transmit side to be able to understand the contents of the frame flowing in each direction, which is a mixture of circuit and packet traffic. It is assumed that the frames have the configuration described in European Patent Application No. 854500266. By definition and for a given line speed, the medium frame is nearly constant in duration. The medium frame duration is: Nc x BT < NF * 125 microsec < (Nc+1) x BT

_ where Nc is the number of bits in the frame, and BT is the bit time. As a consequence, the number of bits per frame is equal to a constant Nc+0 or +1 bit. At the receiving side, the number of bits is counted in a counter. If Nc is equal to X bits, and since it is not known whether X is the high value (Nc+1) or the low value (Nc), then the next frame may have either X bits, X-1 bits or X+1 bits. Thus, the synchronization is made by observing the recurrence of the flag within these limits of +1 or -1 bit. To control the synchronization of the link, the XMIT component issues a flag at the 125 microsecond clock transition which follows the transmission of Nc bits. The receive side has an Nc counter initialized at each end of flag time, incremented at each bit time, which holds the number of received bits of a frame, and an Nc register, which holds the number of bits of the previous frame and thus represents the supposed number of bits of the present frame. (Clocks have a good accuracy so that the number of bits in a frame does not change very often.) When the contents of the Nc counter and the Nc register are equal, the RCV component verifies where the beginning of a flag is. The flag is detected by its first...