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Chip Wiring Capacitance Measurement

IP.com Disclosure Number: IPCOM000039493D
Original Publication Date: 1987-Jun-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 2 page(s) / 33K

Publishing Venue

IBM

Related People

Landrock, J: AUTHOR [+4]

Abstract

For accurately calculating circuit delays for chips to be developed and for preparing an electrical concept, it is essential to know the wiring capacitance. Accurate calculations are extremely difficult, as the capacitances to be considered depend on a plurality of process-specific factors. Therefore, measurements carried out on special test sites are essential. The figure is a diagram of the proposed measuring method. Two drivers OCD1 and OCD2 are arranged adjacent to each other on a test site to obtain matching electrical characteristics. The two driver outputs are connected to chip pads, ensuring that the two paths to the chip pads have substantially identical capacitance values. Drivers OCD1 and OCD2 are driven by an INPUT pad through a receiver REC and an internal circuit A to avoid long delays.

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Chip Wiring Capacitance Measurement

For accurately calculating circuit delays for chips to be developed and for preparing an electrical concept, it is essential to know the wiring capacitance. Accurate calculations are extremely difficult, as the capacitances to be considered depend on a plurality of process-specific factors. Therefore, measurements carried out on special test sites are essential. The figure is a diagram of the proposed measuring method. Two drivers OCD1 and OCD2 are arranged adjacent to each other on a test site to obtain matching electrical characteristics. The two driver outputs are connected to chip pads, ensuring that the two paths to the chip pads have substantially identical capacitance values. Drivers OCD1 and OCD2 are driven by an INPUT pad through a receiver REC and an internal circuit A to avoid long delays. On the chip, both outputs are connected to the inputs of an XOR gate. The output of OCD2 is subjected only to the wiring capacitance of the OCD2 chip pad path, while the wiring capacitance CW to be measured is additionally connected to the output of OCD1. The additional capacitive load increases the delay of OCD1. As the leading edge of voltage U1 is flatter and the threshold voltage of the XOR gate is reached later than for voltage U2, the XOR gate supplies a pulse, having a width corresponding to the delay difference of the two drivers OCD1 and OCD2, to the OUTPUT pad through driver OCD3 in response to each pulse edge encountered...