Browse Prior Art Database

High-Bandwidth, Low-Contention, Hierarchical Memory Structure

IP.com Disclosure Number: IPCOM000039505D
Original Publication Date: 1987-Jun-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 3 page(s) / 53K

Publishing Venue

IBM

Related People

Lavallee, RW: AUTHOR [+3]

Abstract

This hierarchical memory structure increases transfer bandwidth, greatly reduces contention, and allows much simpler memory management than can otherwise be achieved. Storage hierarchy performance can be dramatically improved by the application of the following concepts at one or more levels in the hierarchy: 1. A physical close-coupling of an adjacent pair of array levels to eliminate cables and to simplify the control structure. Higher performance due to a much wider inter-level bus, lower cost, and lower data management overhead are the advantages. The closest coupling and greatest bandwidth improvement are realizable when adjacent hierarchy levels are implemented on the same physical array chip. 2.

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High-Bandwidth, Low-Contention, Hierarchical Memory Structure

This hierarchical memory structure increases transfer bandwidth, greatly reduces contention, and allows much simpler memory management than can otherwise be achieved. Storage hierarchy performance can be dramatically improved by the application of the following concepts at one or more levels in the hierarchy: 1. A physical close-coupling of an adjacent pair of array levels to eliminate cables and to simplify the control

structure. Higher performance due to a much wider

inter-level bus, lower cost, and lower data management

overhead are the advantages. The closest coupling and

greatest bandwidth improvement are realizable when

adjacent hierarchy levels are implemented on the same

physical array chip. 2. A design in which at least one of the middle levels of the hierarchy features two buffered ports, which

permits this level to perform concurrent operations to

both the next lower and the next higher array levels.

This substantially reduces contention for the data

busses to that level and for memory cycles in that

level. 3. Multiple wideband buffering that permits concurrent

operation to multiple parallel lower levels. These may be applied individually in a design. However, the advantages may be masked by some other "bottleneck" in the storage hierarchy. Applied together, their advantages complement each other. In the first concept, an adjacent pair of hierarchy levels is packaged sufficiently close together to permit the elimination of a cabled bus interconnection. The packaging medium (e.g., module or card) is then capable of supporting a much wider and simpler interconnection that offers greater performance and potentially greater reliability and less cost. Performance improvements are due to the reduced bus propagation delay and the higher data rates due to the wider bus. Cost and reliability are improved by the elimination or simplification of cables, bus controllers, and separate array controllers. The second concept improves performance by reducing contention between the next lower and the next higher levels for a given level's available cycles. It is in the nature of hierarchies that, for a given access data width to the next lower level, a multiple of these are required to the next higher level to complete its full transfer. The multiple ranges from 4 to 512 in existing systems, and it can be a serious performance limitation when array cycle availability is a bottleneck of the storage hierarchy. The second concept proposes a middle level array chip with unique features. A second port on the middle level array chip is proposed that connects directly to the next higher level bus in order to free the normal port for exclusive use of the next lower level accesses.

In support of the new port, the array chip contains a pair of port buffer registers, each sufficiently wide to contain the full transfer width to the next higher level. In addition, the internal organization...