Browse Prior Art Database

Direct Memory Access in a Multitasking Environment

IP.com Disclosure Number: IPCOM000039507D
Original Publication Date: 1987-Jun-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 3 page(s) / 48K

Publishing Venue

IBM

Related People

Bischoff, G: AUTHOR [+3]

Abstract

A technique is described for providing direct memory access (DMA) in a multitasking environment, like that disclosed in [*]. The present embodiment is 7 channels, 3 of which are shown in the figure for simplification. All interface signals 12 are described in the Technical Reference Manual for the IBM Personal Computer XT, IBM Part Number 1502237, and also in the Technical Reference Manual for the IBM Personal Computer AT, IBM Part Number 1502243, both published by IBM Corporation. A DMA intercept logic 14 monitors the address lines 16 on the I/O channel to determine when the DMA controller is being programmed by a requesting device. Address bits A9-A0 go into this logic 14 and are decoded to intercept the control words written to the DMA controller.

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Direct Memory Access in a Multitasking Environment

A technique is described for providing direct memory access (DMA) in a multitasking environment, like that disclosed in [*]. The present embodiment is 7 channels, 3 of which are shown in the figure for simplification. All interface signals 12 are described in the Technical Reference Manual for the IBM Personal Computer XT, IBM Part Number 1502237, and also in the Technical Reference Manual for the IBM Personal Computer AT, IBM Part Number 1502243, both published by IBM Corporation. A DMA intercept logic 14 monitors the address lines 16 on the I/O channel to determine when the DMA controller is being programmed by a requesting device. Address bits A9-A0 go into this logic 14 and are decoded to intercept the control words written to the DMA controller. When the DMA controller is programmed, the two least significant bits of data, along with the particular I/O address written to, indicate which DMA channel is being set up. The four-bit ID currently in use on the XMA card is stored in one of eight four-bit registers 21. The register 21 is selected according to the DMA channel being programmed. The two data bits determine DMA channels 1, 2, or 3, and the address decode determines if the DMA channel is a high or a low group. If it is a high group, channels 1, 2 and 3 are translated to channels 5, 6 and 7. DMA channel 4 is not used in the present embodiment. The translation is done by steering the strobe for storing the ID to the second half of the eight four-bit registers 21. Memory read and write operations continue to use the current ID until the DMA operation actually takes place. The DACK 7 through DACK 0 DMA acknowledge signals on the I/O channel indicate when the DMA read or write operation takes place and on which channel. Whenever a DMA operation takes place, one DMA acknowledge signal goes active, indicating which DMA channel is in use. The DACK signals are use...