Browse Prior Art Database

Management of the RESET Tag to Accommodate Scanner Behavior in a Communication Controller

IP.com Disclosure Number: IPCOM000039511D
Original Publication Date: 1987-Jun-01
Included in the Prior Art Database: 2005-Feb-01
Document File: 2 page(s) / 48K

Publishing Venue

IBM

Related People

Bersac, JM: AUTHOR [+3]

Abstract

In a communication controller comprising a processor P connected to line scanners SC by bus B through a redrive circuit R, commands can be sent to processor P by a service processor SP through an address/command bus LAC (Fig. 1). The line scanners comprise a microprocessor which works under control of a microcode stored into a read-only memory (ROM). The B bus tag-out lines are used to send commands to the line scanners. Among these lines, a RESET tag is activated at the machine power-on to enable the ROM diagnostics. It is activated during the POWER-ON RESET time signal which is sent to P by a line coming from the service processor. Processor P is designed according to the level sensitive scan design (LSSD) technique, and thus comprise LSSD shift register chains which may be loaded from the service processor.

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Management of the RESET Tag to Accommodate Scanner Behavior in a Communication Controller

In a communication controller comprising a processor P connected to line scanners SC by bus B through a redrive circuit R, commands can be sent to processor P by a service processor SP through an address/command bus LAC (Fig. 1). The line scanners comprise a microprocessor which works under control of a microcode stored into a read-only memory (ROM). The B bus tag-out lines are used to send commands to the line scanners. Among these lines, a RESET tag is activated at the machine power-on to enable the ROM diagnostics. It is activated during the POWER-ON RESET time signal which is sent to P by a line coming from the service processor. Processor P is designed according to the level sensitive scan design (LSSD) technique, and thus comprise LSSD shift register chains which may be loaded from the service processor. In operation, a failure can occur between P and a line scanner. At this moment, a LSSD shift is performed in P, and the RESET tag can change because its gating in P is done by the output of other latches of the chain. In this case, the line scanner processor enables its ROM diagnostics, and the content of the ROM is destroyed forbidding any dump. As shown in Fig. 2, the LSSD shift is activated by a decode of the LAC bus. This decode is used to disable the redrive drivers in order to isolate the line scanner from the processor P. It is used to mask the eventual RESET ta...